一种模数混合型LDO的设计  

Design of analog-digital hybrid low dropout regulator

作　　者：程铁栋 刘志福 郭建平 CHENG Tiedong;LIU Zhifu;GUO Jianping(School of Electrical Engineering and Automation,Jiangxi University of Science and Technology,Ganzhou 341000,Jiangxi Province,China;School of Electronics and Information Technology,Sun Yat-sen University,Guangzhou 510006,China)

机构地区：[1]江西理工大学电气工程与自动化学院,江西赣州341000 [2]中山大学电子与信息工程学院,广东广州510006

出　　处：《电子元件与材料》2022年第5期545-550,共6页Electronic Components And Materials

基　　金：国家自然科学基金(61874143);江西理工大学博士科研启动基金(GJJ191206)。

摘　　要：针对传统模拟低压差线性稳压器(LDO)在低电源电压下性能不足等问题,提出了一种模数混合型LDO的设计方法。通过对传统模拟LDO结构中的误差放大器输出端进行信号采样,增加数字控制回路,实现对输出电压的精确控制。提出的LDO基于中芯国际(SMIC)180 nm CMOS工艺设计。仿真结果表明,该LDO在数字控制时钟为1 MHz,输入电源电压为0.9~1.5 V时,输出电压为0.8~1.4 V,最大负载电流为500 mA,静态功耗为75μA,电流效率高达99.9%,负载调整率为1.8%,线性调整率为0.9%。To address the poor performance of traditional analog low dropout(LDO)regulator at low supply voltage,an analog-digital hybrid LDO was proposed.Based on the traditional analog LDO,a digital control loop was added to stabilize the output voltage.The digital control signal of the loop was directly sampled from the output of an error amplifier to realize precise control of the output voltage.The LDO was designed in SMIC 180 nm CMOS process.The simulation results show that at input voltage of 0.9-1.5 V and control clock of 1 MHz,the output voltage,maximum load current,quiescent current and current efficiency of the LDO are 0.8-1.4 V,500 mA,75μA and 99.9%,respectively.The load and linear regulation rate of the LDO are 1.8%and 0.9%,respectively.

关 键 词：低压差线性稳压器 模数混合 大负载电流 低电源电压 

分 类 号：TN432[电子电信—微电子学与固体电子学]