一种适用于DDR存储器控制电路的命令间时序控制验证方案  

A method to verification architecture for command timing control of DDR-memory controller

作　　者：谢宇霆 李海华[1] XIE Yuting;LI Haihua(School of Electronic Information and Electrical Engineering,SJTU,Shanghai 200240,China)

机构地区：[1]上海交通大学电子信息与电气工程学院,上海200240

出　　处：《微电子学与计算机》2022年第6期124-130,共7页Microelectronics & Computer

基　　金：国家自然基金(61574093)。

摘　　要：相变存储器(PCM)作为一种新型存储媒介,具备了高传输速率与非易失性的特点,可以同时满足内存与外存的应用需求,在实际应用中需要根据其特性设计相应的存储器控制电路.本文针对于使用了DDR传输协议的相变存储器读写电路,为满足其验证过程中的时序控制需求,提出了一种适用于PCM控制器的基于通用验证方法(UVM)的验证方案.该方案将命令间时序控制功能从UVM中的序列发生器模块转移到了驱动模块中,通过建立命令队列与时间表来优化这一控制过程,简化了时序判断结构.为了解决PCM读写速度差距导致验证模型数据阻塞的问题,采用了system Verilog中的旗语机制对命令与数据进行了并行化处理,以较简单的代码结构避免了高数据延迟导致后续命令数据发送被阻塞.结果表明,随着UVM中驱动模块的测试用例数从2000个提高到100,000个时,仿真效率提升幅度从20%提高到了127%,大幅提高了仿真效率;并且实现了读延迟期间穿插写命令的数据、命令并行控制效果.本文提出的方案优化了原有控制电路的验证结构,也可以作为各类DDR存储器验证环境的参考.Phase Change Memory(PCM)as a novel memory,has the characteristics of high transmission rate and non-volatility.It can meet the application requirements of both internal and external memory.The memory controller circuit needs to be designed according to its characteristics in the application process.In this paper,a universal verification method(UVM)based verification method for PCM controller using DDR transport protocol is proposed to meet the timing control requirements in the verification process.The method transfers the command timing control function from the sequence module in the UVM to the driver module,simplifies the timing controlling structure by establishing a command queue and time board to optimize this timing control process.To solve the problem of data blocking caused by time gap between PCM’s read and write latency,the semaphore in System Verilog is also applied to parallelize the command and data,which brings a simpler code structure to implement the functionality of avoiding data latency blocking commands.The results show that as the number of test cases in the UVM increases,the boost in simulation efficiency of this method will be improved.When the test case increases from 2,000 to 100,000,the boost in simulation efficiency increases from 20%to 127%.The parallel control of interpolating write command during read latency is also implemented.The method proposed in this paper optimizes the verification structure of original control circuit,while can also be used as a reference to various DDR memory controllers’verification environments.

关 键 词：DDR 验证方法学 时序控制 

分 类 号：TN43[电子电信—微电子学与固体电子学]