基于BCH纠错算法的编解码器设计与实现  

Design and implementation of codec based on BCH error correction algorithm

作　　者：王莞 魏敬和[1,2] 于宗光 Wang Guan;Wei Jinghe;Yu Zongguang(School of IoT Engineering,Jiangnan University,Wuxi 214122,China;China Electronics Technology Group Corporation No.58 Research Institute,Wuxi 214072,China)

机构地区：[1]江南大学物联网工程学院,江苏无锡214122 [2]中国电子科技集团第58研究所,江苏无锡214072

出　　处：《电子技术应用》2022年第5期42-46,共5页Application of Electronic Technique

基　　金：国家自然科学基金(62174150)。

摘　　要：随着NAND Flash存储单元的快速发展,存储密度增加使得器件的出错概率增加,为此提出了一种优化的BCH编解码器结构,编码和解码过程每个时钟周期可以并行处理16位数据,其中译码电路中的伴随式模块、错误位置多项式模块与钱氏(Chien)搜索模块采取三级流水线结构,纠错和检错阶段可以同时进行,有效地提高数据的处理速度和纠错速度。在完成电路的RTL设计后利用VCS工具完成了电路的仿真验证,结果表明在传输8 192 bit数据生成672校检因子情况下实现了48位纠错,工作频率最高支持200 MHz。With the rapid development of NAND Flash memory cells and the increase in storage density, the error probability of devices has increased. For this reason, an optimized BCH codec structure is proposed. The encoding and decoding process can pro-cess 16-bit data in parallel in each clock cycle. Among them, the syndrome module, error location polynomial module and Chien search module in the decoding circuit adopt a three-stage pipeline structure, and the error correction and error detection stages can be carried out at the same time, which effectively improves the data processing speed and error correction speed. After completing the RTL design of the circuit, the simulation verification of the circuit was completed by using the VCS tool. The results showed that 48-bit error correction was achieved when 8 192 bit data was transmitted to generate 672 check factors, and the maximum op-erating frequency was 200 MHz.

关 键 词：NAND Flash BCH码 钱氏搜索 流水线结构 编解码 

分 类 号：TN492[电子电信—微电子学与固体电子学]