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作 者:单春燕 卢新民 蒋东铭 钱峰 周猛 SHAN Chunyan;LU Xinmin;JIANG Dongming;QIAN Feng;ZHOU Meng(Nanjing Electronic Devices Institute,Nanjing,210016,CHN;Nanjing Guobo Electronics Company Limited,Nanjing,211100,CHN)
机构地区:[1]南京电子器件研究所,南京210016 [2]南京国博电子股份有限公司,南京211100
出 处:《固体电子学研究与进展》2022年第2期130-134,共5页Research & Progress of SSE
摘 要:基于0.18μm SOI CMOS工艺研制了一款高集成度的天线调谐器芯片,该芯片集成了射频开关、电容阵列和数模混合控制电路,面积仅为1433μm×760μm。芯片核心射频电路由5 bit电容阵列和SP3T射频开关并联组成,其中电容阵列采用了基于射频开关的二进制加权并行结构,具有较高的电容值调节精度和调谐比。测试结果表明:电容阵列的电容值由0.3 pF步进到3.4 pF,每级步进0.1 pF,最大品质因数为36@1 GHz,SP3T开关的直流导通电阻为1Ω,关断电容为180 fF@2.7 GHz,插入损耗为0.86 dB@2.7 GHz,输入功率为35 dBm时的二次谐波和三次谐波分别为-62 dBm和-57 dBm。Based on 0.18μm SOI CMOS process,a highly integrated antenna tuner chip was developed.The chip integrates RF switch,capacitor array and mixed digital-analog control circuit,and its area is only 1433μm×760μm.Core RF circuit of the chip was composed of 5 bit capacitor array and SP3T RF switch in parallel.The capacitor array adopted binary-weighted parallel structure based on RF switch,which had high capacitance regulation accuracy and high tuning ratio.The test results show that the capacitance of capacitor array can be digitally programmed from 0.3 pF to 3.4 pF in 0.1 pF steps and shows a maximum quality factor of 36 at 1 GHz.For the SP3T switch,the DC on-resistance is 1Ω,off-capacitance is 180 fF at 2.7 GHz,insert loss is 0.86 dB at 2.7 GHz and the second harmonic and third harmonic are-62 dBm and-57 dBm when driven by 35 dBm signal.
分 类 号:TN432[电子电信—微电子学与固体电子学]
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