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作 者:Quan Pan Xiongshi Luo Zhenghao Li Zhengzhe Jia Fuzhan Chen Xuewei Ding C.Patrick Yue
机构地区:[1]School of Microelectronics,Engineering Research Center of Integrated Circuits for Next-Generation Communications,Ministry of Education,Southern University of Science and Technology,Shenzhen 518055,China [2]Department of Electronic and Computer Engineering,Hong Kong University of Science and Technology,Hong Kong SAR,China [3]ZTE Microelectronics,Shenzhen 518055,China
出 处:《Journal of Semiconductors》2022年第7期68-77,共10页半导体学报(英文版)
基 金:supported in part by Research and Development Program in Key Areas of Guangdong Province under Grant 2019B010116002;in part by the National Natural Science Foundation of China under Grant 62074074;in part by the Science and Technology Plan of Shenzhen under Grants JCYJ20190809142017428 and JCYJ20200109141225025。
摘 要:This paper presents a 26-Gb/s CMOS optical receiver that is fabricated in 65-nm technology. It consists of a tripleinductive transimpedance amplifier(TIA), direct current(DC) offset cancellation circuits, 3-stage gm-TIA variable-gain amplifiers(VGA), and a reference-less clock and data recovery(CDR) circuit with built-in equalization technique. The TIA/VGA frontend measurement results demonstrate 72-dB? transimpedance gain, 20.4-GHz-3-dB bandwidth, and 12-dB DC gain tuning range. The measurements of the VGA’s resistive networks also demonstrate its efficient capability of overcoming the voltage and temperature variations. The CDR adopts a full-rate topology with 12-dB imbedded equalization tuning range. Optical measurements of this chipset achieve a 10-12 BER at 26 Gb/s for a 2;-1 PRBS input with a-7.3-dBm input sensitivity. The measurement results with a 10-dB @ 13 GHz attenuator also demonstrate the effectiveness of the gain tuning capability and the built-in equalization. The entire system consumes 140 mW from a 1/1.2-V supply.
关 键 词:clock and data recovery EQUALIZER optical receiver transimpedance amplifier variable-gain amplifier
分 类 号:TN929.1[电子电信—通信与信息系统]
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