基于UVM的SoC系统级外设验证平台设计  

The Design of SoC System-level peripheral Verification Platform Based on UVM

作　　者：杜越[1] 郑杰良 吴益然 DU Yue;ZHENG Jie-liang;WU Yi-ran(The 54th institution of China Electronics Technology Group Corporation)

机构地区：[1]中国电子科技集团公司第五十四研究所

出　　处：《中国集成电路》2022年第6期37-43,共7页China lntegrated Circuit

摘　　要：SoC芯片集成了众多外设接口,其外设的系统级验证工作已成为SoC芯片开发的瓶颈之一。本文在分析了SoC外设验证的特点与需求的基础上,提出了一种基于UVM验证方法学的SoC系统级外设验证平台.该验证平台支持UVM环境与软件程序的握手以及软件程序的调试信息打印。以I2C接口模块的系统级验证为例进一步介绍了该平台的搭建和用例开发,实践表明,所提出的验证平台易于搭建,切合SoC外设验证的特点和需求,能够成功地完成外设模块的SoC系统级验证,可有力支撑SoC整体验证工作的开展。As System On Chip(SOC)usually integrates many peripheral interfaces,system-level verification of peripherals has become one of the bottlenecks in the SoC design.According to the analysis of the characteristics and requirements of SoC peripheral verification,this paper presents a system-level peripheral verification platform based on Universal Verification Methodology(UVM).The verification platform supports both handshaking between verification environment and software,and printing debugging information of software.Taking the system-level verification of the I2C module as an example,this paper further introduces the construction of the platform.Experiments show that the proposed verification platformis easy to construct,and meets the requirements of SoC peripheral verification.The platformcan successfully carry out corresponding system-level tests,which strongly supports the overall verification of SoC.

关 键 词：SOC 系统级验证 UVM 外设 软硬件协同仿真 

分 类 号：TN47[电子电信—微电子学与固体电子学]