基于宏块的HEVC编码器数据存取架构  

The HEVC encoder data access architecture based on macroblock

作　　者：黄霖 施隆照[1] 付文恺 HUANG Lin;SHI Long-zhao;FU Wen-kai(College of Physics and Information Engineering)

机构地区：[1]福州大学物理与信息工程学院

出　　处：《中国集成电路》2022年第6期44-50,77,共8页China lntegrated Circuit

摘　　要：新一代视频编码标准(High Efficiency Video Coding,HEVC)与AVC/H.264相比,在相同视觉质量条件下可以节省50%的码率,但HEVC视频编码器的FPGA硬件实现非常复杂,对视频数据存取要求非常高,特别是编码所需的原始图像和参考图像数据的存取。本文根据HEVC的CTU块编码流程,提出了一种满足高效编码器实时编码所需数据的存取实现方案,给编码器实现实时编码创造有利条件,实现了HEVC视频编码器所需数据的高效稳定的读写。整个设计在VCS仿真环境上验证了读写逻辑的正确性,并在Intel公司的Arria10型号FPGA板上通过了在线测试。测试结果表明,在DDR4接口工作在266 MHz频率下,按本文设计的存储器架构可以满足编码器实现1080P120@fps的编码所需数据的读写。Compared with AVC/H.264,the new generation video coding standard(High Efficiency Video Coding,HEVC)can save 50%bit rate under the same visual quality.However,the FPGA hardware implementation of HEVC video encoder is very complex and has a very high requirement for video data access,especially the access of original image and reference image data required for coding.According to the CTU block coding process of HEVC,this paper proposes an access implementation scheme to meet the requirements of the data required for real-time coding of efficient encoder,creates favorable conditions for the encoder to realize real-time coding,and realizes the efficient and stable reading and writing of the data required by HEVC video encoder.The whole design verifies the correctness of the read-write logic in the VCS simulation environment,and passes the online test on the aria 10 FPGA board of Intel company.The test results show that the memory architecture designed in accordance with the paper can meet the requirement for reading and writing data required for 1080P120@fps encoding of encoder when DDR4 interface works at 266MHz frequency.

关 键 词：视频编码 数据传输 DDR FPGA 

分 类 号：TN919.81[电子电信—通信与信息系统] TP333[电子电信—信息与通信工程]