面向超高速以太网ADB-DMA的设计与实现  

DESIGN AND IMPLEMENTATION OF ADB-DMA FOR ULTRA HIGH SPEED ETHERNET

作　　者：吴剑箫 王鹏[3,4] Wu Jianxiao;Wang Peng(Shanghai Advanced Research Institute,Chinese Academy of Sciences,Shanghai 200120,China;University of Chinese Academy of Sciences,Beijing 100049,China;School of Computer Engineering and Science,Shanghai University,Shanghai 200444,China;State Key Lab of Mathematical Engineering and Advanced Computing,Wuxi 214215,Jiangsu,China)

机构地区：[1]中国科学院上海高等研究院,上海200120 [2]中国科学院大学,北京100049 [3]上海大学计算机工程与科学学院,上海200444 [4]数学工程与先进计算国家重点实验室,江苏无锡214215

出　　处：《计算机应用与软件》2022年第6期116-120,共5页Computer Applications and Software

基　　金：数学工程与先进计算国家重点实验室开放基金项目(2019A05)。

摘　　要：传统以太网DMA(Direct Memory Access)控制器基于描述符配置、更新与中断处理,百G速率下对处理器性能提出巨大挑战。提出并介绍一种自适应双缓冲DMA(Adaptive Dual-Buffered Direct Memory Access,ADB-DMA)结构、原理及实现,最大程度降低对处理器的打扰,具有吞吐率高、兼容性好、总线利用率高等优点。该DMA方案可应用于以太网、PCIe、SRIO等高速接口协议,目前已成功应用于国产芯片100 G以太网接口。Traditional direct memory access(DMA)controller in Ethernet is based on descriptor configurations,update and interrupt processing,which brings a huge challenge to the performance of processor at the speed of over 100 Gbit/s.This paper proposes and introduces the structure,working principle and implementation of an adaptive dual-buffered direct memory access(ADB-DMA),which minimizes the disturbance to the processor and has the advantages of high throughput,good compatibility and high bus utilization.The DMA scheme can be applied to Ethernet,PCIe,SRIO and other high-speed interface protocols.It has been successfully applied to 100 G Ethernet interface of domestic chip.

关 键 词：超高速以太网 自适应双缓冲DMA DMA控制器 

分 类 号：TP3[自动化与计算机技术—计算机科学与技术] TN492[电子电信—微电子学与固体电子学]