超大尺寸芯片封装内应力的改善  

Improvement of Internal Stress in Ultra-Large Chip Package

作　　者：侯耀伟 王喆 乔志壮 杜勿默 周扬帆 Hou Yaowei;Wang Zhe;Qiao Zhizhuang;Du Wumo;Zhou Yangfan(The 13th Research Institute,CETC,Shijiazhuang 0500511 China)

机构地区：[1]中国电子科技集团公司第十三研究所,石家庄050051

出　　处：《半导体技术》2022年第6期498-502,共5页Semiconductor Technology

摘　　要：为改善超大尺寸芯片封装的内应力,研究了使用导电胶粘接的超大尺寸芯片的陶瓷封装结构,建立了简化的结构模型。模型从上到下依次为硅芯片、导电胶和陶瓷基板三层结构。利用有限元分析方法,研究了导电胶的粘接层厚度、弹性模量、热膨胀系数和固化温度对芯片封装内应力的影响。结果表明,粘接层所受的应力主要集中在导电胶和芯片粘接界面边缘处,且粘接层四个角所受的应力最大,故在贴片工艺中要保证导电胶在芯片四个角的溢出,防止芯片脱落。适当增加导电胶的粘接层厚度,选取低弹性模量和低热膨胀系数的导电胶,以及采用较低的固化温度可大幅度降低器件的内应力,提高芯片剪切力。In order to reduce the internal stress in ultra-large chip package,the ceramic package structure of ultra-large chip bonded with conductive adhesive was studied,and a simplified structure mo-del was established.The model is a three-layer structure which consists of a silicon chip,conductive adhesive and a ceramic substrate from top to bottom.The effects of bonding layer thickness,elastic modulus,thermal expansion coefficient and curing temperature of the conductive adhesive on the internal stress of the chip package were studied by using finite element analysis method.The results show that the stress on the bonding layer is mainly concentrated at the edge of the bonding interface between the conductive adhesive and the chip,and the stress on the four corners of the bonding layer is the largest.So the overflow of conductive adhesive at the four corners of the chip should be guaranteed during the die bonding process to prevent the chip from falling off.Increasing the bonding layer thickness of the conductive adhesive appropriately,selecting the conductive adhesive of low elastic modulus and low thermal expansion coefficient,and adopting a lower curing temperature can greatly reduce the internal stress of the device and improve the shear force of the chip.

关 键 词：芯片封装 内应力 贴片工艺 固化温度 弹性模量 

分 类 号：TN305.94[电子电信—物理电子学] TN405