一种高性能极化码SC译码器设计  

Design of a High-Performance SC Decoder for Polar Codes

作　　者：王晓蕾[1] 戴吴骏 杜高明[1] 李桢旻 张多利[1] WANG Xiaolei;DAI Wujun;DU Gaoming;LI Zhenmin;ZHANG Duoli(Institute of VLSI Design,Hefei University of Technology,Hefei 230601,China)

机构地区：[1]合肥工业大学微电子设计研究所,安徽合肥230601

出　　处：《电子科技》2022年第8期14-20,共7页Electronic Science and Technology

基　　金：国家重点研发计划(2018YFB2202604);安徽省高校协同创新项目(GXXT-2019-030)。

摘　　要：针对极化码SC译码器存在的高延时、低吞吐率、低资源效率等问题,文中提出了一种高性能SC译码器硬件架构。通过剪枝冻结比特结点的方式化简SC译码二叉树,设计跨周期的PE单元存储模块,并在译码最后一个阶段利用2b-SC算法,保证译码器具有较低的延时和较高的吞吐率。采用资源复用的方法,提高译码器资源效率。测试结果表明,文中所提出的译码器周期为330,吞吐率为388.85 Mbit·s-1,资源效率为2.204 Mbit·s-1·kGE-1。与其他SC译码器的对比试验表明,该高性能SC译码器的延时、吞吐率、资源效率均得到了有效改善。此外,该译码器的功耗较低,应用前景良好。In view of high latency,low throughput and low area efficiency of polar code SC decoder,a high-performance hardware architecture of SC decoder is proposed.The decoder becomes low-latency and high-throughput by pruning frozen bit nodes to simplify the SC decoding binary tree,designing cross-cycle storage for PE,and using 2b-SC algorithm in the last stage.The resource-reused method is adopted to increase the decoder area efficiency.The testing results show that the cycle of the proposed decoder is 330,the throughput is 388.85 Mbit·s,and the area efficiency is 2.204 Mbit·s·kGE.Compared with other SC decoders,latency,throughput and area efficiency of the high-performance SC decoder proposed in this study are significantly improved.Additionally,the decoder has lower power consumption and broad application prospect.

关 键 词：极化码 串行抵消 延时 功耗 吞吐率 资源效率 资源复用 专用集成电路 

分 类 号：TN47[电子电信—微电子学与固体电子学]