一种基于动态反相放大器的低功耗Σ-Δ ADC  

A Low Power Σ-Δ ADC Based on Floating Inverter Amplifier

作　　者：林宏凯 陈群超[1] LIN Hongkai;CHEN Qunchao(College of Physics and Information Engineering,Fuzhou University,Fuzhou 350116,P.R.China)

机构地区：[1]福州大学物理与信息工程学院,福州350116

出　　处：《微电子学》2022年第2期236-239,共4页Microelectronics

基　　金：国家自然科学基金资助项目(92064006)。

摘　　要：设计了一种低功耗Σ-ΔADC。该ADC采用三阶前馈1 bit的结构。为了降低功耗,开关电容积分器的OTA采用动态反相放大器,其具有低功耗、全动态工作、全差分的电路结构、稳定共模点无需CMFB等优点。在SMIC 0.18μm CMOS工艺下的仿真结果表明,在20 kHz带宽内,4 MHz的采样时钟下,信噪失真比(SNDR)可以达到91.9 dB,动态范围(DR)达到101 dB,有效位数约为15 bit。在1.2 V电源电压下,整体功耗为78μW。A low power Σ-Δ analog-to-digital converter with a third-order feed-forward 1 bit architecture was designed. In order to reduce power consumption, the OTA of the switched capacitor integrator used a floating inverter amplifier, which had the advantages of low power consumption, dynamic operation, fully differential circuit structure and stable common mode point without the need for CMFB. Fabricated in a SMIC 180 nm CMOS process, the prototype modulator achieved 91.9 dB signal-to-noise-and-distortion ratio(SNDR), 93 dB signal-to-noise ratio(SNR), 101 dB dynamic range(DR), and 15 bit effective number of bit(ENOB) over a 20 kHz signal bandwidth with 4 MHz sampling frequency. The circuit consumed only 78 μW at a 1.2 V supply.

关 键 词：Σ-Δ调制器 低功耗 动态反相放大器 动态比较器 

分 类 号：TN792[电子电信—电路与系统]