一种高能效相位量化ADC的设计  

Design of a High Efficiency Phase Quantization A/D Converter

作　　者：陈红梅[1] 王学锐 万方莉 尹勇生[1,2] CHEN Hongmei;WANG Xuerui;WAN Fangli;YIN Yongsheng(Institute of VLSI Design,Hefei Univ.of Technol.,Hefei 230601,P.R.China;IC Design Web-Cooperation Research Center of MOE,Hefei Univ.of Technol.,Hefei 230601,P.R.China)

机构地区：[1]合肥工业大学微电子设计研究所,合肥230601 [2]合肥工业大学教育部IC设计网上合作研究中心,合肥230601

出　　处：《微电子学》2022年第2期240-245,共6页Microelectronics

基　　金：模拟集成电路国家级重点实验室基金资助项目(6142802190506);安徽省科技攻关计划项目(202104g01020008);安徽高校协同创新项目(GXXT-2019-030)。

摘　　要：设计了一种基于电荷重分配式逐次逼近的高能效相位量化模数转换器(PH ADC)。针对传统结构中量化电平线性度差导致转换精度低的问题,建立相位映射关系,并采用线性回归曲线技术,提升了比较电平线性度。同时,比较电平数量缩减为传统结构的一半,降低了电路的电容阵列面积、功耗和复杂度。进一步地,引入低功耗的单调开关切换方式和共模电压提升电路,将被加权的比较电平提高至电源电压,避免了设计额外的参考电平产生电路。基于55 nm CMOS工艺的电路仿真结果表明,在全工艺角条件下,有效位数达5.6位以上,FOM值达24.38 fJ/conv。A high energy efficiency phase quantization A/D converter(PH ADC)based on successive approximation of load redistribution was designed.Aiming at the problem of low conversion accuracy caused by poor linearity of quantization level in traditional structure,the linearity of comparison level was improved by establishing phase mapping relationship and adopting linear regression curve technology.At the same time,the number of comparison levels was reduced to half of the traditional structure,which reduced the capacitor array area,power consumption and complexity of the circuit.Furthermore,a low power monotonic switching mode and a common-mode voltage lifting circuit were introduced to raise the weighted comparison level to the supply voltage,avoiding the design of additional reference level generating circuits.The circuit simulation results based on 55 nm CMOS process showed that the ENOB was more than 5.6 bit and the FOM value was 24.38 fJ/conv under the whole process corner condition.

关 键 词：相位量化模数转换器 线性度 映射关系 线性回归 

分 类 号：TN792[电子电信—电路与系统]