一种应用于中频数字化接收的连续/离散时间混合结构带通Σ-ΔADC  

A Hybrid Continuous/Discrete Time BandpassΣ-ΔADC for IF-Digitizing

作　　者：张沁枫 冯凯 石春琦[2] 张润曦[2] 叶明远 ZHANG Qinfeng;FENG Kai;SHI Chunqi;ZHANG Runxi;YE Mingyuan(58th Research Institute,China Electronics Technology Group Corp.,Wuxi,Jiangsu 200235,P.R.China;Institute of Microelectronic Circuits and Systems,East China Normal University,Shanghai 200241,P.R.China)

机构地区：[1]中国电子科技集团公司第五十八研究所,江苏无锡200235 [2]华东师范大学微电子电路与系统研究所,上海200241

出　　处：《微电子学》2022年第2期246-252,共7页Microelectronics

基　　金：国家自然科学基金资助项目(62174149);江苏省自然科学基金资助项目(BK20211042)。

摘　　要：设计了一种应用于中频数字化接收的基于连续/离散时间混合结构带通Σ-ΔADC。调制器采用六阶带通多比特量化结构,环路滤波器由两个连续时间谐振器和一个离散时间谐振器组成。采用电容数字校准技术将LC连续时间谐振器和RC连续时间谐振器的谐振频率校准至ADC中心频率f_(clk)/8。量化器采用3 bit Flash ADC实现。同时,使用数据加权平均算法对反馈DAC单元之间的失配进行校准。整体中频数字化接收机基于0.18μm SiGe BiCMOS工艺设计。后仿真结果表明,在3.3 V电源电压下,当采样时钟频率f_(clk)为18 MHz且过采样率为45时,该Σ-ΔADC消耗21 mW的功耗,在200 kHz的带宽范围内获得89 dB的信噪比和95 dB的无杂散动态范围。A bandpassΣ-ΔADC with a continuous/discrete time hybrid structure for IF-digitizing was designed.The modulator adopted a sixth-order bandpass multi-bit quantization structure,and the loop filters of the modulator included two continuous time resonators followed by a discrete time resonator.The use of capacitor based digital calibration technology enabled the accurate calibration of resonance frequencies of the LC resonator and RC resonator to be f_(clk)/8 precisely.The quantizer was realized by a 3 bit flash ADC.At the same time,DWA algorithm was used to calibrate the mismatch between feedback DAC units.The overall IF-digitizing receiver was fabricated in a 0.18μm SiGe BiCMOS process.The post-simulation results showed that theΣ-ΔADC consumed 21 mW under a 3.3 V power supply voltage.With a f_(clk)of 18 MHz and an OSR of 45,a SNR of 89 dB and a SFDR of 95 dB could be obtained within the 200 kHz signal bandwidth.

关 键 词：Σ-ΔADC LC谐振器 连续时间谐振器 开关电容谐振器 多比特量化器 

分 类 号：TN432[电子电信—微电子学与固体电子学] TN792