基于0.13μm SiGe BiCMOS工艺的12位1.6 GS/s折叠插值A/D转换器  

A 12 bit 1.6 GS/s Folding and Interpolating A/D Converter Based on 0.13 μm SiGe BiCMOS Process

作　　者：邹沛哲 王永禄[2,3] 易周 ZOU Peizhe;WANG Yonglu;YI Zhou(College of Optoelec.,Chongqing Univ.of Posts and Telecommun.,Chongqing 400065,P.R.China;National Laboratory of Science and Technology on Analog Integrated Circuit,Chongqing 400060,P.R.China;The 24th Research Institute of China Electronics Technology Corporation.,Chongqing 400060,P.R.China)

机构地区：[1]重庆邮电大学光电学院,重庆400065 [2]模拟集成电路国家级重点实验室,重庆400060 [3]中国电子科技集团公司第二十四研究所,重庆400060

出　　处：《微电子学》2022年第2期301-305,共5页Microelectronics

基　　金：模拟集成电路国家级重点实验室基金资助项目(6142802180101)。

摘　　要：提出了一种基于0.13μm SiGe BiCMOS工艺的高速、高精度折叠插值A/D转换器。采用基于SEF开关的新型采样/保持电路,固定保持阶段电压,实现了高速、高精度、高线性度的信号采样。采用带有射极跟随器的折叠放大器,构成平均折叠和环形插值的四级级联结构,减少了比较器数目,降低了建立时间和整体功耗。采用新型两级比较器,将模拟与数字信号进行隔离,优化了回踢噪声。使用小尺寸晶体管,减小了再生时间。在3.3/5 V电源和0.13μm SiGe BiCMOS工艺下,该折叠插值A/D转换器实现了1.6 GS/s的采样率,SFDR为71.3 dB,SNDR为63.6 dB,ENOB为10.27 bit。A high speed and high precision folding and interpolating A/D converter based on 0.13 μm SiGe BiCMOS process was proposed. A new sampling/holding circuit based on SEF switch was adopted to fix the voltage in the holding stage, thus realizing signal sampling with high speed, high precision and high linearity. The folding amplifier with emitter follower was adopted to form a four-level cascade structure of average folding and annular interpolation, which reduced the number of comparators, the settling time and the overall power consumption. A new two-stage comparator was used to isolate analog and digital signals and optimize kickback noise. The use of small size transistors reduced the regeneration time. Under 3.3/5 V power supply and 0.13 μm SiGe BiCMOS process, the folding and interpolating A/D converter achieved a sampling rate of 1.6 GS/s, a SFDR of 71.3 dB, a SNDR of 63.6 dB and a ENOB of 10.27 bit.

关 键 词：采样/保持电路 折叠放大器 比较器 折叠和插值ADC 高速 

分 类 号：TN792[电子电信—电路与系统]