分离真伪时钟的处理器FPGA原型性能校准方法  

A performance calibration method of processor FPGA prototyping by separating real and pseudo wall clock

作　　者：郑雅文 吴瑞阳 陈天奇 汪文祥 章隆兵[1,2,3] 王剑 ZHENG Yawen;WU Ruiyang;CHEN Tianqi;WANG Wenxiang;ZHANG Longbing;WANG Jian(State Key Laboratory of Computer Architecture,Institute of Computing Technology,Chinese Academy of Sciences,Beijing 100190;Institute of Computing Technology,Chinese Academy of Sciences,Beijing 100190;University of Chinese Academy of Sciences,Beijing 100049;Loongson Technology Corporation Limited,Beijing 100190)

机构地区：[1]计算机体系结构国家重点实验室(中国科学院计算技术研究所),北京100190 [2]中国科学院计算技术研究所,北京100190 [3]中国科学院大学,北京100049 [4]龙芯中科技术有限公司,北京100190

出　　处：《高技术通讯》2022年第5期462-470,共9页Chinese High Technology Letters

基　　金：国家科技重大专项(2019ZX01029101-006)资助项目。

摘　　要：针对现场可编程门阵列(FPGA)原型系统中内存刷新频率过高导致内存延迟变大的问题,提出了一种校准处理器FPGA原型系统性能的方法,搭建了一个精确的FPGA原型性能验证平台,可用于硅前快速准确地评估处理器系统性能。问题的根本原因是FPGA原型系统同时存在真实墙上时钟和由运行频率降低导致的伪墙上时钟,且在内存系统中刷新和访问请求分别按照两个时钟进行,然而真实机器上这两种请求都是按照真墙上时钟进行,因此FPGA内存系统有性能误差。本文通过将两个墙上时钟分离来实现校准,该校准方法准确度高、通用性强,校准后的FPGA原型系统运行SPEC CPU 2006基准测试程序性能分值平均误差由7.49%降至0.36%,最高误差降至2%以下,可快速有效地指导硅前性能优化。Aiming at the problem that memory refresh rate is too high in field programmable gate array(FPGA)prototype system,which leads to large memory latency,a method to calibrate the performance of FPGA prototype system is proposed in this paper,and an accurate FPGA prototype performance verification platform is built,which can be used to quickly and accurately evaluate processor system performance before silicon.The root cause of the problem is that the FPGA prototype system has both a real wall clock and a pseudo wall clock caused by the decrease of running frequency,and the refresh and access requests in the memory system are carried out according to two clocks respectively.However,the two requests in the real machine are carried out according to the real wall clock,so the FPGA memory system has performance errors.In this paper,two wall clocks are separated to achieve the calibration.The calibration method has high accuracy and strong versatility.The average error of the performance score of the calibrated FPGA prototype system running SPEC CPU2006 benchmark program is reduced from 7.49%to 0.36%,and the maximum error is reduced to less than 2%,which can quickly and effectively guide the pre-silicon performance optimization.

关 键 词：硅前验证 现场可编程门阵列(FPGA)原型 内存系统 性能评估 校准方法 

分 类 号：TN791[电子电信—电路与系统] TP332[自动化与计算机技术—计算机系统结构]