基于FPGA+ARM多路千兆以太网通信接口设计  被引量:5

Design of multi⁃channel Gigabit Ethernet communication interface based on FPGA+ARM

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作  者:李杨 苏和平 张丹 许乔 LI Yang;SU Heping;ZHANG Dan;XU Qiao(School of Computer Science and Information Engineering,Hubei University,Wuhan 430062,China)

机构地区:[1]湖北大学计算机与信息工程学院,湖北武汉430062

出  处:《现代电子技术》2022年第15期25-29,共5页Modern Electronics Technique

摘  要:针对现有的千兆以太网通信接口设计中存在的价格昂贵、不能胜任多路以太网传输等问题,提出并实现一种基于FPGA+ARM的多路千兆以太网通信接口模块。该设计分为ARM和FPGA两个部分,通过STM32微处理器带有的灵活静态存储控制器(FSMC)接口进行数据交换。ARM部分通过发送函数、接收函数实现对以太网接口控制以及对数据的处理;FPGA部分采用自顶向下的设计方法,通过时序转换模块、打包解包模块以及MAC控制模块实现以太网接口功能,并且定义了两个自定义协议,分别用于ARM与FPGA通信以及FPGA内部打解包模块与MAC控制模块的通信。搭建了硬件测试验证平台对设计进行了全面验证。硬件测试验证结果表明该设计能够正确实现以上功能。该方案成本低廉、扩展性强、支持多通道传输且支持网络风暴抑制,适用于对成本要求较高且需多通道以太网传输的场景。The existing design of the Gigabit Ethernet communication interface is expensive and incompetent in the multi⁃channel Ethernet transmission,so a multi⁃channel Gigabit Ethernet communication interface module based on FPGA+ARM is proposed and implemented.This design is composed of two parts,that is,ARM and FPGA,which exchange data by the flexible static memory controller(FSMC)interface of the STM32 microprocessor.In the part of the ARM,the Ethernet interface control and data processing are achieved by sending function and receiving function.In the part of the FPGA,the top⁃down design method is adopted to achieve the Ethernet interface functions by the time series conversion module,packaging and unpacking module,and MAC control module.In addition,two self⁃defined protocols are confirmed for the communication between ARM and FPGA,and the communication between the FPGA internal packaging⁃unpacking module and MAC control module.A hardware test verification platform was set up to verify the design fully.The validation results show that the design can properly implement the above functions.The solution is of low cost and high scalability.In addition,it supports multi⁃channel transmission and network storm suppression,so it is suitable for high cost and multi⁃channel Ethernet transmission.

关 键 词:多路千兆以太网 FPGA+ARM FSMC 时序转换模块 打包解包模块 MAC控制模块 数据帧 通信协议 

分 类 号:TN919-34[电子电信—通信与信息系统] TP393.11[电子电信—信息与通信工程]

 

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