基于UVM的远程控制FPGA一体化闭环仿真验证平台  

Design of Remote Control FPGA Closed-loop Simulation Verification Platform Based on UVM

作　　者：于清华 高赛军 YU Qinghua;GAO Shaijun(Shanghai Aerospace Electronic Communication Equipment Research Institute,Shanghai 201109,China)

机构地区：[1]上海航天电子通讯设备研究所,上海201109

出　　处：《计算机测量与控制》2022年第7期304-309,共6页Computer Measurement &Control

摘　　要：远程控制FPGA是卫星执行地面指令和转发地面数据的核心部分,且该FPGA使用的帧协议较为复杂,帧传输数据协议数据格式变化多样;为了对远程控制FPGA进行充分的验证,以提高FPGA软件的可靠性,避免存在设计隐患,提出了一种使用目前较先进的通用验证方法学UVM建立了一体化闭环仿真验证平台用来测试远程控制FPGA;仿真结果表面,该验证平台具有带约束收敛的测试向量随机生成和自动检查输出结果正确性功能,能够进行功能覆盖率检测,并有效提高远程控制FPGA验证的效率和质量,较好地满足了验证需求。Remote control Field Programmable Gata Array(FPGA)is the core part of satellite to execute ground instruction and transmit ground data,and the frame protocol used by FPGA is complex,and the format of frame transmission data protocol varies widely.In order to fully verify the remote control FPGA,improves the reliability of FPGA software and avoids the hidden design problems,an integrated closed-loop simulation verification platform is established to test the remote control FPGA using the advanced Universal Verification Methodology(UVM).The simulation results show that the verification platform has the functions of test vector random generation with the constraint convergence,which automatically check of the correctness of the output results.It can detect the function coverage and effectively improve the efficiency and quality of remote control FPGA verification,which better meets the verification requirements.

关 键 词：UVM 远程控制 FPGA 验证平台 DUT 

分 类 号：TP3[自动化与计算机技术—计算机科学与技术]