RISCV架构的一种指令自动对齐电路  

An Instruction Antomatic Aligning Circuit Based on RISCV

作　　者：刘德 魏敬和 高营 Liu De;Wei Jinghe;Gao Ying(No.58 Research Institute,China Electronics Technology Group Corporation,Wuxi 214072,China)

机构地区：[1]中国电子科技集团公司第五十八研究所,无锡214072

出　　处：《单片机与嵌入式系统应用》2022年第8期32-36,41,共6页Microcontrollers & Embedded Systems

基　　金：江苏省产业前瞻与关键核心技术重点项目(BE2019003)。

摘　　要：基于RISCV指令集架构实现了一种指令自动对齐电路。该电路可以将指令缓存发送过来的32位指令数据进行分解,从中解析出正确的指令。当指令缓存发送过来的32位指令数据对应的地址不是4字节对齐时(地址的低两位不是00)时,该电路可以自动将下一拍取指令数据的地址对齐到4字节,同时给出指令是否有效的指示标识;当指令地址4字节对齐时,该电路对指令数据进行分析,给出指令有效的标识、指令和对应指令的实际地址。给出的指令对齐电路的延时为4级两输入逻辑门,适用于高频标量处理器的前端取指令电路。Based on RISC-V instruction architecture, this article implements an instruction aligning circuit.This circuit can recognize and output the correct instruction by analyzing the 32-bit instruction data passed from the I-Cache.When the address of the 32-bit instruction data is not aligned with 4-Byte, say the two least significant bits of the address is not equal to 00,this circuit automatically aligns the address of the next instruction-fetching with 4-Byte and output the signal that indicating whether the instruction is valid or invalid.When the address of the instruction data is aligned with 4-Byte, this circuit presents the instruction, the real address of this instruction, and indicates that the instruction is valid.The latency of the circuit for aligning the instruction address to 4-Byte presented in this article is 4 levels of 2-inputs logic gates, which is very useful for the front-end instruction fetch circuit of high frequency scalar processor.

关 键 词：RISCV 指令对齐 微架构 内核流水线 

分 类 号：TP322[自动化与计算机技术—计算机系统结构]