基于FPGA的CAN总线控制器全模式应用设计  

Full Mode Application Design of CAN Bus Controller Based on FPGA

作　　者：郁文君 张恒 唐渊 Yu Wenjun;Zhang Heng;Tang Yuan(CHINA KEY SYSTEM&INTEGRATED CIRCUIT CO.,LTD.,Wuxi 214072,China)

机构地区：[1]中科芯集成电路有限公司,无锡214072

出　　处：《单片机与嵌入式系统应用》2022年第8期87-91,共5页Microcontrollers & Embedded Systems

摘　　要：基于独立的CAN总线控制器SJA1000,在Intel和Motorola两种接口控制时序下的BasicCAN和PeliCAN模式的应用设计研究,为汽车、船舶、航天等大规模使用CAN总线进行数据传输的领域提供了多种应用设计方案。采用型号为EP4CE10F17C8N的FPGA对SJA1000寄存器读写时序、数据发送和接收逻辑的设计以及与上位机通信、数据校验方法。通过FPGA模块和SJA1000模块组合,设计SJA1000使用Intel或者Motorola接口控制时序时数据收发功能的Verilog程序,利用CAN分析仪和上位机软件进行数据交互、数据校验试验,实现了FPGA对SJA1000在BasicCAN和PeliCAN模式下的寄存器初始化和数据收发功能,并且在与上位机进行交互数据时确保了数据的实时性和正确性。Based on the application design of the independent can bus controller SJA1000 in the BasicCAN and PeliCAN modes under the two interface timing of Intel and Motorola, this paper provides a variety of application design schemes for the fields of large-scale data transmission using CAN bus, such as automobile, ship, aerospace and so on.The FPGA with model EP4 CE10 F17 C8 N is used to design the SJA1000 register reading and writing timing, data sending and receiving logic, as well as the communication with the host computer and data verification method.Through the combination of FPGA module and SJA1000 module, the Verilog program of data sending and receiving function when SJA1000 uses Intel or Motorola interface timing is designed, and the data interaction and data verification test are carried out by using CAN analyzer and host computer software.The register initialization and data sending and receiving functions of SJA1000 in BasicCAN and PeliCAN modes are realized by FPGA,and the real-time and correctness of the data are ensured when interacting with the host computer.

关 键 词：SJA1000 Intel时序 Motorola时序 BasicCAN模式 PeliCAN模式 EP4CE10F17C8N 

分 类 号：TN92[电子电信—通信与信息系统]