基于递归通用信号延迟叠加算子的单相锁相环  

Single-phase phase-locked loop based on recursive implementation of generalized delayed signal superposition

作　　者：刘勇[1] 杨涛[1] 盘宏斌[1] 曾力[1] 曹雷 LIU Yong;YANG Tao;PAN Hongbin;ZENG Li;CAO Lei(School of Automation and Electronic Information,Xiangtan University,Xiangtan 411105,China;Duyun Power Supply Bureau,Guizhou Power Grid Co.,Ltd.,Duyun 558000,China)

机构地区：[1]湘潭大学自动化与电子信息学院,湖南湘潭411105 [2]贵州电网有限责任公司都匀供电局,贵州都匀558000

出　　处：《电力系统保护与控制》2022年第14期172-180,共9页Power System Protection and Control

基　　金：国家自然科学基金项目资助(51577162);湖南省自然科学基金项目资助(2021JJ30674)。

摘　　要：当电网电压存在谐波与直流偏移时,传统锁相环无法精确锁相。为此,提出一种基于递归通用信号延迟叠加算子的改进单相锁相环算法。该方法在锁相环前级引入递归通用信号延迟叠加算子,以产生正交信号并滤除谐波。接着在两相静止坐标系下,构建延迟采样周期滤波器,通过将正交分量延迟两个采样周期的方法抑制直流偏移。所提单相锁相环技术能够消除直流偏移和谐波干扰的影响,快速准确地获取基波和所需的特定次谐波信息,同时具有良好的动态性能和稳定性。最后,仿真与实验结果证明了该方法的可行性。When there are harmonics and DC offset in a grid voltage,the traditional phase-locked loop(PLL)cannot accurately realize phase lock.Hence,an improved single-phase phase-locked loop algorithm based on recursive-form generalized delayed signal superposition(RGDSS)operators is proposed.To produce the orthogonal signals and filtering of the harmonic,RGDSS operators are introduced into the pre-stage of the PLL.Then in a two-phase stationary reference frame,a delayed sampling period filter is constructed to suppress the DC offset by delaying the orthogonal component by two sampling periods.The proposed PLL,which has good dynamic performance and stability,can effectively eliminate the influence of DC offset and harmonics,and obtain the fundamental and desired harmonic information quickly and accurately.Finally,the feasibility of the method is verified by simulation and experiment.

关 键 词：单相锁相环 延迟信号叠加 直流偏移 谐波分离 同步信号检测 

分 类 号：TM935[电气工程—电力电子与电力传动] TN713[电子电信—电路与系统]