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作 者:夏晓娟[1,2] 庄玉成 易磊 杨琨 XIA Xiaojuan;ZHUANG Yucheng;YI Lei;YANG Kun(College of Electronic and Optical Engineering&College of Microlectronics.Nanjing University of Posts and Tele-communications,Nanjing.210023,CHN;National and Local Join1 Engineering Laboralory for RF Integration and Micro-Assembly Technology,Nanjing Universilty of Posts and Telecommunications,Nanjing,210023,CHN;Nanjing Micro Electronics Inc,Nanjing,210042,CHN)
机构地区:[1]南京邮电大学电子与光学工程学院微电子学院,南京210023 [2]南京邮电大学射频集成与微组装技术国家地方联合工程实验室,南京210023 [3]南京微盟电子有限公司,南京210042
出 处:《固体电子学研究与进展》2022年第3期207-213,共7页Research & Progress of SSE
基 金:航空科学基金资助项目(20182412)。
摘 要:设计了一款可吐纳3 A大电流的跟踪终端线性稳压器。该稳压器采用双电源供电,降低了芯片的功耗。内部误差放大器采用轨到轨输入结构设计,拓展了稳压器输入共模电压范围;同时采用跨导线性环电路结构和简单补偿电路结构的设计,使其在负载突变时提供快速的负载瞬态响应,减小输出过冲。输出级上下功率管采用NMOS推挽式输出,可提供1 A/2 A/3 A的大电流,极大提高了稳压器的带载能力。该稳压器能够满足DDRⅠ/Ⅱ/Ⅲ和低功耗DDRⅢ/Ⅳ总线终端对电源供应的要求。采用华虹0.35μm工艺流片,在两个输入电压V_(IN)、V_(LDOIN)分别为5 V、2.5 V条件下进行测试,输出/吸收3 A负载电流时,输出稳定在1.25 V。A tracking terminal linear regulator that could accept 3 A high current was designed.Dual power supplies were adopted in this regulator,which reduced power consumption of the chip.The internal error amplifier adopts the design of rail-to-rail input structure,which expands the input common-mode voltage range of the regulator;at the same time,the error amplifier adopts the design of trans-conducting loop circuit structure and simple compensation circuit structure to provide fast load transient response and reduce output overshoot when the load changes. The upper and lower power tubes of the output stage adopt NMOS push-pull output,which can provide a large current of 1 A/2 A/3 A and greatly improve the load capacity of the regulator. This regulator can meet the power supply requirements of DDRⅠ/Ⅱ/Ⅲ and low-power DDRⅢ/Ⅳ bus terminals.The Hua Hong 0.35 μm process is used for tape-out and the test is performed under the input voltage V_(IN) of 5 V and the input voltage V_(LDOIN) of 2.5 V. The output keeps stable 1.25 V voltage with the output/absorption of 3 A load current.
分 类 号:TN432.2[电子电信—微电子学与固体电子学]
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