基于FPGA的万兆以太网UDP_IP硬件协议栈设计与实现  

Design and implementation of 10G ethernet UDP/IP hardware protocol stack based on FPGA

作　　者：董永吉[1] 王钰 袁征[1] Dong Yongji;Wang Yu;Yuan Zheng(PLA Strategic Support Force Information Engineering University,Zhengzhou 450002,China)

机构地区：[1]解放军战略支援部队信息工程大学,郑州450002

出　　处：《计算机应用研究》2022年第8期2465-2468,共4页Application Research of Computers

基　　金：国家重点研发计划资助项目。

摘　　要：针对传统基于软件的协议栈无法满足高速数据传输处理需求的问题,提出了一种基于硬件加速的UDP协议栈设计方案,该方案基于硬件高效并行的特点,实现了UDP/IP协议栈,满足了万兆以太网数据高带宽传输的需求。通过实际测试表明,该设计最高可以达到9.32 Gbps传输速率,满足10 Gbps带宽下线速处理的需求,与传统软件实现相比,处理能力更接近理论极限。Aiming at the problem that the traditional software protocol stack can not meet the performance requirement of high-speed data transmission,this paper presented a design scheme of UDP protocol stack based on hardware acceleration.The design was based on the characteristics of efficient and parallel hardware to implement the UDP/IP protocol stack.And it solved the problem of poor performance of high-speed data transmission.The actual test shows that the design can reach the highest level.To 9.32 Gbps transmission rate,it meets the need of 10 Gbps bandwidth downlink speed processing.Compared with traditional software implementation,it shows that the processing capacity of the proposed method is closer to the theoretical limit.

关 键 词：FPGA 万兆以太网 硬件协议栈 UDP协议 

分 类 号：TP393[自动化与计算机技术—计算机应用技术]