基于门控时钟技术的时钟树低功耗研究  

Research for Clock Tree Low-power Based on Clock-gating Technology

作　　者：陈力颖[1,2] 胥世俊 吕英杰 Chen Liying;Xu Shijun;LüYingjie(School of Electronic and Information Engineering,Tiangong University,Tianjin 300387,China;Tianjin Key Laboratory of Optoelectronic Detection Technology and Systems,Tianjin 300387,China;Tianjin Pengxiang Huaxia Technology Co Ltd,Tianjin 300450,China)

机构地区：[1]天津工业大学电子与信息工程学院,天津300387 [2]天津市光电检测技术与系统重点实验室,天津300387 [3]天津鹏翔华夏科技有限公司,天津300450

出　　处：《南开大学学报（自然科学版）》2022年第3期21-25,共5页Acta Scientiarum Naturalium Universitatis Nankaiensis

基　　金：中国国家留学基金资助(201908120039);天津市应用基础与前沿技术研究计划项目(15JCYBJC16300)。

摘　　要：以TSMC 40 nm工艺为基础,使用Synopsys最新布局布线工具ICCII进行时钟树综合.首先利用传统门控时钟技术来降低时钟树动态功耗,在此基础上,提出了一种有别于传统门控时钟技术的新方法.实验结果表明,传统门控时钟方法在两种不同的场景(scenario)下分别降低动态功耗75.36 mW和136.84 mW,虽然不同scenario降低的动态功耗值不同,但是降低功耗的效果是一样的,降低幅度均为22%.新方法又可以进一步降低34.05 mW的动态功耗,降低幅度为12.5%,低功耗效果显著.By inserting a clock-gating cell,it is possible to turn off the unnecessary clock flip of flipflop,thereby reducing clock network power.Based on the TSMC 40 nm process,Synopsys’latest place and route tool ICCII are used for clock tree synthesis,using traditional clock-gating technology to reduce clock tree dynamic power.A new method different from the traditional clock-gating technology is proposed.The experimental results show that the traditional clock-gating approach reduced dynamic power by 75.36mW and 136.84 mW respectively under different scenarios.Although the dynamic power of different scenarios is different,the effect of reducing power is the same,with a reduction of 22%.The new method can further reduce the dynamic power by 34.05 mW,with a reduction of 12.5%.

关 键 词：门控时钟 低功耗 时钟树 物理设计 

分 类 号：TN47[电子电信—微电子学与固体电子学]