低硬件成本256点FFT处理器的IP核设计  

Design of IP Core of Low Hardware-Cost 256-Point FFT Processor

作　　者：于建[1] 范浩阳 YU Jian;FAN Haoyang(Physics and Electronic Engineering College,Hebei Normal University for Nationalities,Chengde 067000,China)

机构地区：[1]河北民族师范学院物理与电子工程学院,承德067000

出　　处：《数据采集与处理》2022年第4期917-925,共9页Journal of Data Acquisition and Processing

基　　金：河北省自然科学基金(F2020101001);河北省引进留学人员资助项目(C20210301);河北省承德市科学技术研究与发展计划(202001B014);河北民族师范学院科学技术研究项目(PT2019026)。

摘　　要：设计了一种基于现场可编程门阵列(Field programmable gate array,FPGA)的低硬件成本256点快速傅里叶变换(Fast Fourier transform,FFT)处理器的IP核。采用按频率抽取的基⁃24算法和单路延迟负反馈(Single⁃path delay feedback,SDF)流水线架构用于减少旋转因子的复数乘法运算复杂度。为了降低硬件成本,提出了一种串接正则有符号数(Canonical signed digit,CSD)常数乘法器取代常用的布斯乘法器用来完成旋转因子W^(i)_(256)与对应序列的复数乘法运算,同时这种乘法器还能够移除存储旋转因子系数的只读存储器(Read only memory,ROM)。该处理器IP核基于QUARTUS PRIME平台进行综合,在Cyclone 10LP FPGA上实现。结果显示,该FFT处理器最高工作频率为100 MHz,对于24位符号数FFT运算,逻辑单元(Logic elements,LEs)使用量与记忆体位(Memory bits,MBs)使用量仅为3978 LEs和6456 MBs。An IP core of low hardware⁃cost 256⁃point fast Fourier transform(FFT)processor is designed based on field programmable gate array(FPGA).In order to reduce the complexity of twiddle factor calculation,the radix⁃24 algorithm based on decimation in frequency and the single⁃path delay feedback(SDF)pipelined architecture are adopted.For reducing hardware⁃cost,a cascade canonical signed digit(CSD)complex multiplier instead of conventional Booth multiplier is proposed for the operation of twiddle factor W^(i)_(256) multiplied by the corresponding sequences.Also,the proposed cascade CSD multiplier can remove read only memory(ROM)for storing coefficients of twiddle factors.The IP core is synthesized by using QUARTUS PRIME tool and is implemented on Cyclone 10LP FPGA.The result shows that the proposed FFT design can work under a maximum clock frequency of 100 MHz which occupies only 3978 logic elements(LEs)and 6456 memory bits(MBs)hardware⁃resource for 24⁃bit signed number FFT operation.

关 键 词：快速傅里叶变换 旋转因子 串接CSD常数乘法器 流水线架构 硬件成本 

分 类 号：TN47[电子电信—微电子学与固体电子学]