可扩展的数字电路在线演化架构设计  

Design of extended architecture on intrinsic evolvable hardware for digital circuits

作　　者：聂鑫 李元香[2] NIE Xin;LI Yuan-xiang(School of Computer Science and Engineering,Wuhan Institute of Technology,Wuhan 430205,China;School of Computer Science,Wuhan University,Wuhan 430072,China)

机构地区：[1]武汉工程大学计算机科学与工程学院,湖北武汉430205 [2]武汉大学计算机学院,湖北武汉430072

出　　处：《计算机工程与设计》2022年第8期2361-2368,共8页Computer Engineering and Design

基　　金：国家自然科学基金项目(61672391)。

摘　　要：为提高数字电路在线演化过程中的个体多样性以及收敛速度,提出一种函数级电路演化设计与实现方法,将每一个可演化逻辑单元中的函数功能也编码为染色体,参与演化操作,使函数功能在演化过程中也能够动态调整;限制逻辑单元的连接深度,使每一个逻辑单元的可连接深度都较小且相同,有利于抑制非法个体和加快收敛速度;在演化策略中引入一种不等概率连接的变异算子,缩小演化算法的搜索空间。多组测试电路的实验结果表明,该方法在增加生成电路多样性的同时,加快了电路演化的收敛速度,对规模不大的目标电路设计具有优势,特别适合于电路的容错与局部自修复。To improve the individual diversity and convergence speed of intrinsic evolvable hardware,a function-level evolutionary design approach of circuit was present.The functionality in each evolutionary logical unit was also encoded as chromosome to take part in evolutionary operation,thus the functionality was also dynamically adjusted in the evolutionary process.The connection depth of the logical unit was limited,the connection depth of each logical unit was relatively small with the same depth,which was conducive to curb illegal individual and speeded up the convergence process.Mutation operator with unequal probability was introduced in evolutionary strategy and the mutation operator met the structure of more complex logic circuit,the search space of evolutionary algorithm was reduced.Experiments with multiple test circuit verify that the proposed method increases the diversity of generated circuit,accelerates the convergence speed of the circuit evolution,which shows specialty in small scale goal circuit design,particularly in the local fault-tolerant and self-recovery of circuit.

关 键 词：演化硬件 在线演化 虚拟可重构电路 查找表 现场可编程门阵列 

分 类 号：TP301[自动化与计算机技术—计算机系统结构]