基于FPGA的双乘法器卷积加速算子的封装方法  

Encapsulation method of double multiplier convolution acceleration operator based on FPGA

作　　者：聂煜桐 沈月峰 杨帆[1] 王吕大[1] NIE Yu-tong;SHEN Yue-feng;YANG Fan;WANG Lyu-da(Institute 706,Second Academy of China Aerospace Science and Industry Corporation,Beijing 100854,China)

机构地区：[1]中国航天科工集团第二研究院七〇六所,北京100854

出　　处：《计算机工程与设计》2022年第8期2385-2392,共8页Computer Engineering and Design

摘　　要：FPGA因其灵活性、高并行性和可定制性,在卷积神经网络的加速中表现出良好的性能。实践中通常会将卷积的乘加运算交付给FPGA的DSP块,因此DSP的使用效率会直接影响加速器的性能。将两个乘法操作封装到一个DSP块可以同时提高DSP资源的利用率和卷积运算的速度。符号校准电路解决双乘法器封装带来的符号问题,使其支持的运算扩展到双有符号数,扩大算子对激活函数的支持范围。通过将卷积运算展开成向量内积的方式,进一步提高运算的并行度。FPGA shows good performance in the acceleration of convolutional neural networks because of its flexibility,high parallelism and customizability.In practice,the multiplication and addition operation of convolution is usually delivered to DSP block of FPGA,so the efficiency of DSP directly affects the performance of accelerator.Encapsulating the two multiplication operations into one DSP block improved the utilization of DSP resources and the speed of convolution operation.The symbol calibration circuit solved the symbol problem caused by the double multiplier,made the supporting operations extend to double signed numbers,and enlarged the range of the activation functions.By expanding convolution operation into vector inner pro-duct,the parallelism of operation was further improved.

关 键 词：卷积算子 可编程逻辑门阵列 加速器 双乘法 符号校验 循环展开 并行 

分 类 号：TP398.1[自动化与计算机技术—计算机应用技术]