I2C主从通信协议扩展驱动设计  

I2C Master-slave Communication Protocol Expansion Driver Design

作　　者：严寒 方振国[1] 汪珺 郭伟 毛春雨 YAN Han;FANG Zhenguo;WANG Jun;GUO Wei;MAO Chunyu(School of Physics and Electronic Information,Huaibei Normal University,Huaibei Anhui 235000,China)

机构地区：[1]淮北师范大学物理与电子信息学院,安徽淮北235000

出　　处：《佳木斯大学学报（自然科学版）》2022年第4期39-42,共4页Journal of Jiamusi University：Natural Science Edition

基　　金：教育部产学研项目(2019ITA01041);安徽省质量工程项目(2020jyxm1668,JY19003);安徽省基层教研室示范项目(2020SJSFJXZZ350)。

摘　　要：针对I2C总线协议缺少主机与多个地址相同器件之间的通信协议规定,且总线传输速率不能自适应调节的问题,提出了一种基于FPGA的I2C扩展通信协议设计方法。设计了低速、中速、高速三个速率通道,并对器件地址相同的模块进行编码,多路片选控制模块将I2C数据通过选择的速率通道传递给选通从机模块。该方法以4块器件地址相同的AT24C02EEPROM为从机,在100Kbps,400Kbps,3.4Mbps传输速率下进行了设计验证,完全达到了设计要求。Aiming at the problem that the I2Cbus protocol lacks the communication protocol regulations between the host and multiple devices with the same address.The bus transmission rate can’t be adjusted adaptively,an FPGA-based I2Cextended communication protocol design method is proposed.Three rate channel,low-speed,medium-speed,and high-speed are designed,and modules with the same device address are encoded.The multi-channel chip select control module transmits I2Cdata to the strobe slave module through the selected rate channel.This method uses 4 AT24C02EEPROMs with the same device address as slaves,and carries out design verification at a transmission rate of100Kbps,400Kbps,and 3.4Mbps,which fully meets the design requirements.

关 键 词：I2C扩展协议 FPGA 主从通信 传输速率 

分 类 号：TN915[电子电信—通信与信息系统]