Cache Memory Design for Single Bit Architecture with Different Sense Amplifiers  

作　　者：Reeya Agrawal Anjan Kumar Salman A.AlQahtani Mashael Maashi Osamah Ibrahim Khalaf Theyazn H.H.Aldhyani 

机构地区：[1]VLSI Center of Excellence,GLA University,Mathura,281406,India [2]Computer Engineering Department,Research Chair of New Emerging Technologies and 5G Networks and Beyond,College of Computer and Information Sciences,King Saud University,Saudi Arabia [3]Software Engineering Department,King Saud University,Riyadh,11543,Saudi Arabia [4]Al-Nahrain University,Al-Nahrain Nano-Renewable Energy Research Center,Baghdad,Iraq [5]Applied College in Abqaiq,King Faisal University,Al-Ahsa,31982,Saudi Arabia

出　　处：《Computers, Materials & Continua》2022年第11期2313-2331,共19页计算机、材料和连续体（英文）

基　　金：Research General Direction funded this research at Universidad Santiago de Cali,Grant Number 01-2021 and APC was funded by 01-2021.

摘　　要：Most modern microprocessors have one or two levels of on-chip caches to make things run faster,but this is not always the case.Most of the time,these caches are made of static random access memory cells.They take up a lot of space on the chip and use a lot of electricity.A lot of the time,low power is more important than several aspects.This is true for phones and tablets.Cache memory design for single bit architecture consists of six transistors static random access memory cell,a circuit of write driver,and sense amplifiers(such as voltage differential sense amplifier,current differential sense amplifier,charge transfer differential sense amplifier,voltage latch sense amplifier,and current latch sense amplifier,all of which are compared on different resistance values in terms of a number of transistors,delay in sensing and consumption of power.The conclusion arises that single bit six transistor static random access memory cell voltage differential sense amplifier architecture consumes 11.34μW of power which shows that power is reduced up to 83%,77.75%reduction in the case of the current differential sense amplifier,39.62%in case of charge transfer differential sense amplifier and 50%in case of voltage latch sense amplifier when compared to existing latch sense amplifier architecture.Furthermore,power reduction techniques are applied over different blocks of cache memory architecture to optimize energy.The single-bit six transistors static random access memory cell with forced tack technique and voltage differential sense amplifier with dual sleep technique consumes 8.078μW of power,i.e.,reduce 28%more power that makes single bit six transistor static random access memory cell with forced tack technique and voltage differential sense amplifier with dual sleep technique more energy efficient.

关 键 词：Current differential sense amplifier(CDSA) voltage differential sense amplifier(VDSA) voltage latch sense amplifier(VLSA) current latch sense amplifier(CLSA) charge-transfer differential sense amplifier(CTDSA) new emerging technologies 

分 类 号：TN722[电子电信—电路与系统]