An Energy-Efficient 12b 2.56 MS/s SAR ADC Using Successive Scaling of Reference Voltages  

作　　者：Hojin Kang Syed Asmat Ali Shah HyungWon Kim 

机构地区：[1]Department of Electronics Engineering,College of Electrical and Computer Engineering,Chungbuk National University,Cheongju,28644,Korea [2]Department of Electrical and Computer Engineering,COMSATS University Islamabad,Abbottabad Campus,Abbottabad,22060,Pakistan

出　　处：《Computers, Materials & Continua》2022年第7期2127-2139,共13页计算机、材料和连续体（英文）

基　　金：supported by Institute of Information&communications Technology Planning&Evaluation(IITP)grant funded by the Korea government(MSIT)(No.2020-0-01304,Development of Self-learnable Mobile Recursive Neural Network Processor Technology);also supported by the MSIT(Ministry of Science and ICT),Korea,under the Grand Information Technology Research Center support program(IITP-2020-0-01462);supervised by the IITP(Institute for Information&communications Technology Planning&Evaluation)”;And also financially supported by the Ministry of Small and Medium-sized Enterprises(SMEs)and Startups(MSS),Korea,under the“Regional Specialized Industry Development Plus Program(R&D,S3091644)”;supervised by the Korea Institute for Advancement of Technology(KIAT);supported by the AURI(Korea Association of University,Research institute and Industry)grant funded by the Korea Government(MSS:Ministry of SMEs and Startups).(No.S2929950,HRD program for 2020).

摘　　要：This paper presents an energy efficient architecture for successive approximation register(SAR)analog to digital converter(ADC).SAR ADCs with a capacitor array structure have been widely used because of its simple architecture and relatively high speed.However,conventional SAR ADCs consume relatively high energy due to the large number of capacitors used in the capacitor array and their sizes scaled up along with the number of bits.The proposed architecture reduces the energy consumption as well as the capacitor size by employing a new array architecture that scales down the reference voltages instead of scaling up the capacitor sizes.The proposed 12-bit SAR ADC is implemented in Complementary Metal Oxide Semiconductor(CMOS)0.13 um library using Cadence Virtuoso design tool.Simulation results and mathematical model demonstrate the overall energy savings of up to 97.3%compared with conventional SAR ADC,67%compared with the SAR ADC with split capacitor,and 35%compared with the resistor and capacitor(R&C)Hybrid SAR ADC.The ADC achieves an effective number of bits(ENOB)of 11.27 bits and consumes 61.7 uW at sampling rate of 2.56 MS/s,offering an energy consumption of 9.8 fJ per conversion step.The proposed SAR ADC offers 95.5%reduction in chip core area compared to conventional architecture,while occupying an active area of 0.088 mm2.

关 键 词：Low voltage low power successive approximation register analog to digital converter switching energy 

分 类 号：TN432[电子电信—微电子学与固体电子学]