基于M-LVDS总线的机载通信系统数字时钟设计与实现  

Design and Implementation of Digital Clock for Airborne Communication System based on M-LVDS Bus

作　　者：向习莲 XIANG Xilian(Southwest China Institute of Electronic Techinology,Shuan 610036,China)

机构地区：[1]中国西南电子技术研究所,四川610036

出　　处：《电子技术（上海）》2022年第6期1-3,共3页Electronic Technology

摘　　要：阐述对机载通信系统中各类数据链时钟精度的要求,系统100MHz时钟精度需达到10-8量级。机载通信系统采用综合机架,机箱背板基材选用、信号线层叠设计、信号线短桩设计等因素均会影响100MHz的时钟的传输精度和抖动。基于M-LVDS总线传输技术,提出一种综合机箱的复杂背板高精度时钟传输的设计方法。通过仿真及实物测试表明,该设计方法能够满足机载通信系统各数据链功能对100MHz系统时钟的高精度和低抖动等指标的需求。According to the requirement analysis of clock precision of various data links in airborne communication system,the system clock precision of 100MHz should reach the level of 10-8.The airborne communication system usually uses an integrated frame,of which the selection of chassis backplane base material,signal line stacking design and signal line short pile design have an important influence on the transmission precision and jitter of 100MHz clock.To solve this problem,this paper proposes a design method of high precision clock transmission for complex backplane of integrated chassis based on M-LVDS bus transmission technology.Simulation and physical test show that this design method can meet the requirements of high precision and low jitter of 100MHz system clock for each data link function of airborne communication system.

关 键 词：通信系统 数据时钟 高精度 低抖动 层叠设计 M-LVDS总线 

分 类 号：TN914.3[电子电信—通信与信息系统] V243[电子电信—信息与通信工程]