基于Xilinx UltraScale+ VU9P FPGA的SoC原型验证系统研究  

Research on SoC Prototype Verification System Based on Xilinx UltraScale+VU9P FPGA

作　　者：丁岩 王一鸣 DING Yan;WANG Yiming(The 47th Institute of China Electronics Technology Group Corporation,Shenyang 110000,China)

机构地区：[1]中国电子科技集团公司第四十七研究所,沈阳110000

出　　处：《微处理机》2022年第4期30-33,共4页Microprocessors

摘　　要：为应对SoC设计规模增大、功能复杂化带来的芯片验证耗时太长的问题,通过讨论SoC系统与FPGA原型核心板资源的架构,按照从ASIC到FPGA的移植原理,设计实现一种基于Xilinx UltraScale+VU9P FPGA的原型验证系统。系统基于Xilinx Vivado工具完成逻辑综合、实现,并完成硬件子系统设计。使用逻辑电平转换器芯片,将FPGA原型的1.8V转换为SoC设计IO为3.3V电平的PAD,实现对3.3V标准电平的兼容。通过实验,在该系统上完成了大规模高性能SoC的软硬件协同验证,结果表明系统实现设计预期功能,有助于加快芯片整体的验证速度。To solve the problem that the chip verification takes too long due to the increasing design scale and complicated functions of SoC,a prototype verification system based on Xilinx UltraScale+VU9P FPGA is designed and implemented by discussing the architecture of SoC system and FPGA prototype core board resources and according to the principle of transplanting from ASIC to FPGA.Based on Xilinx Vivado tool,the system completes logic synthesis,realization and hardware subsystem design.The level shifter chip is used to convert the 1.8V of FPGA prototype into the PAD with the 3.3V level of SoC design IO,which is compatible with the 3.3V standard level.Through the experiment,the hardware and software co-verification of large-scale high-performance SoC is completed on the system.The results show that the system realizes the expected function of the design,which is helpful to speed up the whole verification speed of chips.

关 键 词：SOC设计 FPGA原型验证 软硬件协同验证 

分 类 号：TN47[电子电信—微电子学与固体电子学]