检索规则说明:AND代表“并且”;OR代表“或者”;NOT代表“不包含”;(注意必须大写,运算符两边需空一格)
检 索 范 例 :范例一: (K=图书馆学 OR K=情报学) AND A=范并思 范例二:J=计算机应用与软件 AND (U=C++ OR U=Basic) NOT M=Visual
作 者:张华夏 陈青山[1] 王艳林[1] Zhang Huaxia;Chen Qingshan;Wang Yanlin(School of Instrument Science and Optoelectronic Engineering,Beijing Information Science and Technology University,Beijing 100192,China)
机构地区:[1]北京信息科技大学仪器科学与光电工程学院,北京100192
出 处:《电子测量技术》2022年第13期54-58,共5页Electronic Measurement Technology
基 金:国防军工重点计量科研项目(JSJL2019208B001)资助。
摘 要:为了提高数字式光谱仪的测量效率,研究并实现一种基于FPGA+ARM架构和两级数据缓存的嵌入式高速数据采集与处理技术。采用FPGA为高速A/D转换器提供采样时钟,采样数据由FIFO进行一级缓存,实现跨时钟域的数据传输。采用ARM外围设置的动态数据随机存储器(DDR3)完成二级缓存,解决由于数据实时处理相对偏慢所造成的数据传输堵塞、丢失等问题。实验测试表明数据传输稳定可靠,采集速率可达65 MHz,传输速率最高可达25.6 Mbytes/s,归一化光谱强度误差小于0.5%。可推广应用于具有大吞吐量嵌入式数据采集与实时计算处理需求的精密仪器与设备。In order to improve the measurement efficiency of digital spectrometer,an embedded high-speed data acquisition and processing technology based on FPGA+ARM architecture and two-level cache is investigated and implemented.The FPGA is used to provide a sampling clock for a high-speed A/D converter.The sampled data is then cached by a FIFO so as to realize cross clock domain data transmission.A DDR3 integrated with the ARM is used as a second cache to avoid data jam and loss phenomenon during the high speed transmission due to the relatively slow data processing by the ARM.Experimental tests show that the acquisition rate is up to 65 MHz,and the transmission rate is up to 25.6 Mbytes/s,and the normalized spectral intensity error is less than 0.5%.The achievements present herein can be generalized into such applications as precision instruments,equipment,digital devices and so on,wherein high speed and large throughput data acquisition and real-time data computation are usually indispensable.
分 类 号:TN919.5[电子电信—通信与信息系统]
正在载入数据...
正在载入数据...
正在载入数据...
正在载入数据...
正在载入数据...
正在载入数据...
正在载入数据...
正在链接到云南高校图书馆文献保障联盟下载...
云南高校图书馆联盟文献共享服务平台 版权所有©
您的IP:3.142.243.141