PAM4高速光模块误码测试系统硬件设计  

Hardware Design of PAM4 High-speed Optical Module BERT System

作　　者：胡庆昆 尤青 宋英雄[1] 张倩武[1] Hu Qingkun

机构地区：[1]上海大学特种光纤与光接入网重点实验室,上海200444

出　　处：《工业控制计算机》2022年第8期30-33,共4页Industrial Control Computer

摘　　要：设计了一种兼容NRZ与PAM4信号调制的多通道高速误码测试仪系统方案,支持单通道测试速率为1.25 Gbps~56 Gbps。硬件系统采用Inphi公司ASIC芯片IN015050作为码型发生与接收器,同时设计了专用时钟模块板用于提供差分时钟输入,以及用于扇出光模块信号的夹具板。系统中PCB设计采用高速板材与共面波导结构解决了传输线的信号完整性问题,符合CEI-28G-VSR与OIF-56G-VSR协议规范。所设计的硬件系统经过眼图分析,输出电眼图指标jitter-PP为4.358 ps,均方值jitter-RMS为704.0 fs,搭载DML调制100G-LR4光模块测试光眼图容限为12.5%,PAM4模块误码率低于10-5量级,符合IEEE Std 802.3bs协议标准。This paper designs a multi-channel high-speed BERT(Bit Error Rate Tester)system scheme compatible with NRZ and PAM4 signal modulation,which supports a single-channel test rate of 1.25 Gbps~56 Gbps.The hardware system uses Inphi’s ASIC chip IN015050 as the pattern generator and receiver.At the same time,a dedicated clock module board is designed to provide differential clock input and a fixture board for fan-out optical module signals.In this system,the PCB design uses high-speed material and coplanar waveguide structure to solve the signal integrity problem of the transmission line,and conforms to the CEI-28G-VSR and OIF-56G-VSR protocol specifications.The designed hardware system has undergone eye diagram analysis,the output signal electrical eye diagram index jitter-PP is 4.358ps,the mean square value jitterRMS is 704.0fs,the test optical eye diagram margin of the DML modulate 100G-LR4 optical module is 12.5%,and the bit error rate of the PAM4 module is lower than 10-5magnitude,in line with IEEE Std 802.3bs protocol standard.

关 键 词：PAM4 误码仪 信号完整性 光模块 

分 类 号：TN929.1[电子电信—通信与信息系统]