基于FPGA的多通路SRIO数据传输设计  

A design of multi-channel data transmission with SRIO protocol based on FPGA

作　　者：任勇峰[1] 多卉枫 武慧军[1] Ren Yongfeng;Duo Huifeng;Wu Hujun(National Key Laboratory for Electronic Measurement Technology,North University of China,Taiyuan 030051,China)

机构地区：[1]中北大学电子测试技术国家重点实验室,太原030051

出　　处：《电子测量技术》2022年第14期152-156,共5页Electronic Measurement Technology

摘　　要：为满足航天遥测系统中多路高速数据可靠传输的需求,提出了一种基于FPGA控制器和Serial RapidIO(SRIO)协议的四通路数据传输设计方案。设计使用Xilinx A7系列FPGA,并使用4个其内部集成的SRIO IP核,设计内部逻辑,实现四路SRIO高速数据传输;使用其内部集成的吉比特收发器(GTP)以满足SRIO传输协议物理层要求。硬件电路使用4个高速收发光模块完成光电转换;并使用高质量时钟芯片产生125 MHz的差分时钟信号作为SRIO IP核的参考时钟。经测试验证四路数据传输速率可达440 MB/s,且无丢帧、误码现象,该设计已成功运用于遥测系统某地面测试台项目,可实现四路高速数据稳定传输。In order to meet the requirement of reliable multi-channel high-speed data transmission in space telemetry system, a four-channel data transmission design based on FPGA controller and Serial RapidIO(SRIO) protocol is proposed. Xilinx A7 series FPGA is used in the design, and four SRIO IP cores are used to design the internal logic and realize the high-speed data transmission of four-way SRIO. Use its internal integrated Gigabit transceiver(GTP) to meet the SRIO transport protocol physical layer requirements. The hardware circuit uses four high-speed receiving and luminous modules to complete the photoelectric conversion. A high quality clock chip is used to generate 125 MHz differential clock signal as the reference clock of the SRIO IP core. The data transmission rate of four channels can reach 440 MB/s without frame loss and error. The design has been successfully applied to a ground test platform project of telemetry system, which can realize stable transmission of four channels high-speed data.

关 键 词：可编程逻辑器件(FPGA) Serial RapidIO协议 SRIO IP核 吉比特收发器 共享逻辑 

分 类 号：TN919[电子电信—通信与信息系统]