Flip Chip Die-to-Wafer Bonding Review:Gaps to High Volume Manufacturing  

作　　者：Mario Di Cino Feng Li 

机构地区：[1]Department of Electrical and Computer Engineering,University of Idaho,Moscow,Idaho,83844,USA

出　　处：《Semiconductor Science and Information Devices》2022年第1期8-13,共6页半导体科学与信息器件（英文）

摘　　要：Flip chip die-to-wafer bonding faces challenges for industry adoption due to a variety of technical gaps or process integration factors that are not fully developed to high volume manufacturing(HVM)maturity.In this paper,flip-chip and wire bonding are compared,then flip-chip bonding techniques are compared to examine advantages for scaling and speed.Specific recent 3-year trends in flip-chip die-to-wafer bonding are reviewed to address the key gaps and challenges to HVM adoption.Finally,some thoughts on the care needed by the packaging technology for successful HVM introduction are reviewed.

关 键 词：Flip chip Die-to-Wafer(D2W) Chip-to-Wafer(C2W) Chip-scale packaging(CSP) High volume manufacturing(HVM) Known good die(KGD) Through silicon via(TSV) Reliability 

分 类 号：TP3[自动化与计算机技术—计算机科学与技术]