一种基于时间交织逐次逼近结构的高速低功耗ADC设计  

A high-speed low-power ADC design based on time-interleaved SAR architecture

作　　者：李冬 孙金中 LI Dong;SUN Jin-zhong(The Anhui Siliepoch Technology Co.Ltd)

机构地区：[1]安徽芯纪元科技有限公司

出　　处：《中国集成电路》2022年第8期45-48,51,共5页China lntegrated Circuit

摘　　要：本文介绍了一种采用28nm CMOS工艺实现的12位高速低功耗模数转换器。为了在低功耗的基础上实现高速模数转换,本设计选择时间交织结构为系统架构,单通道ADC采用逐次逼近结构。单通道SAR ADC采样速率90MS/s,4通道时间交织实现360MS/s的采样速率。测试结果表明,该ADC在360MS/s采样速率和33MHz输入信号频率下,测得的信噪失真比(SNDR)和无杂散动态范围(SFDR)分别为62.1dB和71.2dB,功耗为148mW。A 12-bit high-speed low-power ADC was presented and implemented in 28nm CMOS technology.In order to improve the speed of ADC based on the low-power features,the architecture of the presented ADC adopted time-interleaved structure and the single channel adopted successive-approximation-register(SAR)structure.The sampling rate of the single channel was 90MS/s and four sub-channels were interleaved to achieve a sampling rate of 360MS/s.The test results show that the measured SNDR and SFDR of the ADC are 62.1dB and 71.2dB,respectively,for 33MHz input at 360MS/s sample rate.The power consumption of the ADC was 148mW.

关 键 词：模数转换器 时间交织 逐次逼近 低功耗 

分 类 号：TN792[电子电信—电路与系统]