低功耗逐次逼近型模数转换器的设计  

Design of Low-power Successive Approximation Analog-to-digital converter

作　　者：王法翔[1] 周圻坤 WANG Fa-xiang;ZHOU Qi-kun(College of Physics and Information Engineering,Fuzhou University)

机构地区：[1]福州大学物理与信息工程学院

出　　处：《中国集成电路》2022年第8期63-68,共6页China lntegrated Circuit

摘　　要：本文提出了一种低功耗逐次逼近型(Successive Approximation Register,SAR)模数转换器。电路采用MCS切换方式和二级全动态比较器以及可编程时钟产生电路,以实现低功耗的模数转换器。本设计基于SMIC 130 nm CMOS工艺,电源电压为3.3 V,采样速率为2 MS/s,仿真结果表明,ADC的SFDR为77.6 dB,SNDR为59.2 dB,其能达到9.55 bit分辨率,且功耗仅为0.198 mW。This paper presents a low-power Successive Approximation Register(SAR)analog-to-digital converter.The circuit uses MCS switching mode,secondary full dynamic comparator and programmable clock generation circuit to achieve low power consumption analog-to-digital converter.This design is based on SMIC 130 nm CMOS process,power supply voltage is 3.3 V and sampling rate is 2 MS/s,simulation results show that ADC SFDR is 77.6 dB,SNDR is 59.2 dB,it achieves 9.55 bit resolution,and the power consumption is only 0.198 mW.

关 键 词：SAR ADC 二级全动态比较器 MCS切换方式 低功耗 

分 类 号：TN792[电子电信—电路与系统]