基于FPGA的软件锁相环分析与实现  

Analysis and implementation of SPLL based on FPGA

作　　者：康晋[1] 曹旭 姜育生 KANG Jin;CAO Xu;JIANG Yusheng(Yangling Vocational&Technical College,Yangling 712100,China;Shaanxi Northwest Aviation Bidding&Consulting Co.,Ltd.,Xi’an 710065,China;Shaanxi Business College,Xi’an 710119,China)

机构地区：[1]杨凌职业技术学院,陕西杨凌712100 [2]陕西西北民航招标咨询有限公司,陕西西安710065 [3]陕西工商职业学院,陕西西安710119

出　　处：《电子设计工程》2022年第17期37-40,共4页Electronic Design Engineering

摘　　要：针对无线通信网络对时钟的要求,时钟的信号精度直接影响到系统的性能。FPGA芯片自带的Ser Des模块从BBU发送过来的光信号中恢复出数据时钟,VC-TCXO器件产生10 MHz本地时钟,通过FPGA进行鉴相,结合PID算法实现软件锁相,获取一个稳定的10 MHz时钟,并以此时钟作为参考时钟,同步分发给各功能单元使用。结果表明,该软件锁相环动态响应速度快、稳定性高,准确度优于0.05 ppm,已经广泛应用在LTE无线时钟系统中,对5G和NB-IoT等时钟同步要求较高的系统同样有借鉴意义。In view of the requirements of the wireless communication network on the clock,The signal accuracy of the clock directly affects the performance of the system.The Ser Des module that comes with the FPGA chip recovers the data clock from the optical signal sent by the BBU.The VC-TCXO device generates a 10 MHz local clock.The phase is discriminated through the FPGA and combined with the PID algorithm to achieve software phase lock to obtain a stable 10 MHz clock,and use this clock as a reference clock,synchronously distributed to each functional unit for use.The results show that the software phaselocked loop has fast dynamic response speed,high stability,and accuracy better than 0.05 ppm.It has been widely used in LTE wireless clock systems.It can also be used for reference for systems with high clock synchronization requirements such as 5G and NB-IoT.

关 键 词：FPGA LMX2306 软件锁相环(SPLL) 时钟同步 

分 类 号：TN83[电子电信—信息与通信工程]