一种GHz高频应用的低失调高速CMOS动态比较器  

A Low Offset High Speed CMOS Dynamic Comparator for GHz High Frequency Application

作　　者：李恺 王琳 张伟哲 刘博 张金灿 孟庆端 LI Kai;WANG Lin;ZHANG Weizhe;LIU Bo;ZHANG Jincan;MENG Qingduan(Electrical Engineering College,Henan University of Science and Technology,Luoyang,Henan 471023,P.R.China)

机构地区：[1]河南科技大学电气工程学院,河南洛阳471023

出　　处：《微电子学》2022年第3期412-417,共6页Microelectronics

基　　金：国家自然科学基金资助项目(61704049);河南省科技厅科技计划项目(192102210087);河南科技大学研究生质量提升工程项目(2020ZYL-008)。

摘　　要：提出了一种由改进的前置差分运算放大器和差分式锁存器构成的高频、高速、低失调电压的动态比较器。前置预差分放大器采用PMOS交叉互连的负载结构,提升差模增益,进而减小输入失调。后置输出级锁存器采用差分双尾电流源抑制共模噪声,改善输出级失调,并加速比较过程。采用一个时钟控制的开关晶体管替代传统复位模块,优化版图面积,在锁存器中构建正反馈回路,加速了比较信号的复位和输出建立过程。采用65 nm/1.2 V标准CMOS工艺完成电路设计,结合Cadence Spectre工艺角和蒙特卡洛仿真分析对该动态比较器的延时、失调电压和功耗特性进行评估。结果表明,在1.2 V电源电压和1 GHz采样时钟控制下,平均功耗为117.1μW;最差SS工艺角对应的最大输出延迟仅为153.4 ps;1 000次蒙特卡罗仿真求得的平均失调电压低至1.53 mV。与其他比较器相比,该动态比较器的电压失调和高速延时等参数有明显优势。A high frequency, high speed, low offset voltage dynamic comparator, which was composed of an improved pre-differential operational amplifier and a differential latch was proposed. The differential pre-amplifier employed a cross-coupling load structure of paired PMOS transistors to increase the common-mode gain as well as to reduce the input offset voltage. The output-stage latch module used a dual-tail current source to suppress common-mode noise, so as to improve the output offset and speedup the signal comparison. A clock-controlled switching transistor was designed to replace the traditional reset control module, so as to optimize the layout area, while constructing a positive feedback loop to further accelerate the circuit resetting and settling of output comparison signal. A 65 nm/1.2 V standard CMOS process was adopted to implement the circuit design of the proposed dynamic comparator, and the features in terms of delay, offset voltage and power consumption were analyzed and evaluated based on process corner and Monte Carlo simulation by Cadence Spectre tool. The results showed that the average power consumption was 117.1 μW at 1.2 V power supply voltage and 1 GHz input sampling clock. The maximum output delay at the worst SS process corner simulation was only 153.4 ps. The average offset voltage by running 1 000 Monte-Carlo simulations was as low as 1.53 mV. Compared with other comparators, the proposed dynamic comparator had obvious advantages in the performances of voltage offset and high speed delay.

关 键 词：CMOS动态比较器 低失调电压 高速低延时 交叉耦合运算放大器 

分 类 号：TN432[电子电信—微电子学与固体电子学]