基于单端系统时钟信号的ESD软失效研究  

The Research of ESD Soft Failure on Single-ended System Clock Singnals

作　　者：丁燕 李维翰 姚胜 胡剑文 杨丹丹 李岗 Ding Yan;Li Weihan;Yao Sheng

机构地区：[1]合肥联宝信息技术有限公司 [2]合肥产品质量监督检验研究院

出　　处：《安全与电磁兼容》2022年第5期40-44,共5页Safety & EMC

基　　金：2021年度省市场监管局科技计划项目(2021MK017)。

摘　　要：静电放电(ESD)软失效会导致电子产品可靠性变差,产生后续功能性失效。针对这一设计前期难以预测的问题,提出单端系统时钟信号的ESD软失效分析方案,通过计算机系统技术(CST)仿真拟定软失效发生的电流阈值,从而预测软失效发生的可能性。该方案可以在设计前期预测ESD软失效发生的可能性,减少设计修改时间,节约成本,提高研发效率。ESD soft failure can cause poor reliability of electronic products,leading to functional damage in later usage.It is difficult to predict ESD soft failure for its potentiality.To solve this problem,this paper proposes detect ESD soft failure characteristic based on single-ended system clock signals was proposed,and the current threshold of soft failure can be measured by CST simulation,which can predict the possibility of soft failure.The scheme could predict the possibility of soft failure in the early stages of design,which could lessen design modifications and shorten its period,reduce the cost,and improve the efficiency of research and development.

关 键 词：静电放电 软失效 仿真 电流阈值 

分 类 号：TN03[电子电信—物理电子学] O441.1[理学—电磁学]