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作 者:郭超 袁邵祎 武全友 贾勇 Guo Chao;Yuan Shaoyi;Wu Quanyou
机构地区:[1]施耐德电气中国研发中心
出 处:《安全与电磁兼容》2022年第5期45-48,共4页Safety & EMC
摘 要:随着主控芯片时钟频率的逐渐增高,信号完整性成为了传播高速信号首先要考虑的问题。当高速信号需要通过较长的扁平电缆传输时,其特征阻抗的变化就变得尤为重要。由于印制电路板(PCB)的特征阻抗调整具有局限性,扁平电缆平衡端接的特征阻抗无法满足与PCB特征阻抗一致的设计要求。文章首先通过传输线理论计算了扁平电缆平衡端接的特征阻抗;其次,在CST线缆仿真中搭建了平衡与非平衡端接扁平电缆的3D模型,通过仿真得到了平衡与非平衡端接的特征阻抗;再次,通过实例验证了平衡端接扁平电缆特征阻抗的测试值与计算、仿真结果基本一致;最后,在整机系统中验证了仿真得到的非平衡端接的特征阻抗,并解决了原先样机中存在的信号完整性问题。通过对特征阻抗的研究,可以为扁平电缆端接方式提供理论支持。As the clock frequency of master control chips increase gradually,signal integrity has become the primary consideration in high-speed signal transmission.When a long flat cable transmits a high-speed signal,its characteristic impedance holds a particular significance.Due to the limitation of adjusting the characteristic impedance of printed circuit board(PCB),the consistency of characteristic impedance between PCB and balancing-terminated flat cable can be hardly satisfied in design.This paper firstly calculates the characteristic impedance of balancing-terminated flat cable based on transmission line theory.Secondly,balanced and unbalanced terminated flat cable 3D models are built in CST cable simulation platform.Characteristic impedances are obtained.Thirdly,simulation results of balancing-terminated flat cable's characteristic impedance are verified by real tests,and the real result is basically consistent with the calculated and simulated results.Finally,the characteristic impedance of the unbalanced terminated obtained by simulation is verified in the complete system,and the signal integrity problem existed in the prototype has been solved.With the help of characteristic impedance study,theoretical support for flat cable termination can be provided.
分 类 号:TN913.32[电子电信—通信与信息系统] TN41[电子电信—信息与通信工程]
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