基于DDR3的高速低功耗通用图像缓存设计  

Design of High-speed and Low-power Universal Memory Based on DDR3

作　　者：姜牟旬 钟国强 杨浩正 邱继军 常玉春[1] JIANG Muxun;ZHONG Guo-qiang;YANG Hao-zheng;QIU Ji-jun;CHANG Yu-chun(Dalian University of Technology,Dalian 116620,China)

机构地区：[1]大连理工大学,辽宁大连116620

出　　处：《中国电子科学研究院学报》2022年第7期651-656,共6页Journal of China Academy of Electronics and Information Technology

基　　金：国家自然科学基金资助项目(62027826,11975066);省、市、自治区科技资助项目(2020RT01)。

摘　　要：针对高动态CMOS图像传感器数据采集带宽压力大的需求,提出一种针对大量图像数据的高速低功耗通用缓存设计。该设计的控制核心为FPGA,数据源为高动态CMOS图像传感器,存储芯片为DDR3 SDRAM。通过分支预测、帧率匹配、优化解码、通用配置技术,该设计实现了高速缓存、低功耗以及在线配置存储格式。实际应用中,实现连续图像数据的稳定存储并显示,或指定输出一帧图像任意位置的数据,证明了系统结构的稳定性。通过系统级验证方案,分支预测对上位机的读出速度提升115倍,低功耗技术使电源功耗降低9.73%,通用配置技术准确完成在线配置。Due to the high pressure of high dynamic CMOS image sensor data acquisition bandwidth,a high-speed,low-power and general-purpose cache design for a large amount of image data is proposed.The design uses FPGA as the control core,high dynamic CMOS image sensor as the data source and DDR3 SDRAM as the memory chip.Through the use of branch prediction,inter-frame rate matching,optimized decoding,and general configuration technology,the memory core realizes high-speed cache,low power and online configuration memory format.In practical application,the stable storage and display of continuous image is realized,or the data at any specific position in a frame of image can be outputted,which proves the stability of the system structure.Through the system-level verification scheme,the readout speed of branch prediction to the host computer is increased by 115 times,low-power technology reduces power consumption by 9.73%,universal configuration technology accurately completes online configuration.

关 键 词：图像传感器 DDR3 分支预测 帧率匹配 通用 

分 类 号：TN919.5[电子电信—通信与信息系统]