A deep trench super-junction LDMOS with double charge compensation layer  

作　　者：Lijuan Wu Shaolian Su Xing Chen Jinsheng Zeng Haifeng Wu 

机构地区：[1]Hunan Provincial Key Laboratory of Flexible Electronic Materials Genome Engineering,School of Physics&Electronic Science,Changsha University of Science&Technology,Changsha 410114,China

出　　处：《Journal of Semiconductors》2022年第10期103-108,共6页半导体学报（英文版）

摘　　要：A deep trench super-junction LDMOS with double charge compensation layer(DC DT SJ LDMOS)is proposed in this paper.Due to the capacitance effect of the deep trench which is known as silicon-insulator-silicon(SIS)capacitance,the charge balance in the super-junction region of the conventional deep trench SJ LDMOS(Con.DT SJ LDMOS)device will be broken,resulting in breakdown voltage(BV)of the device drops.DC DT SJ LDMOS solves the SIS capacitance effect by adding a vertical variable doped charge compensation layer and a triangular charge compensation layer inside the Con.DT SJ LDMOS device.Therefore,the drift region reaches an ideal charge balance state again.The electric field is optimized by double charge compensation and gate field plate so that the breakdown voltage of the proposed device is improved sharply,meanwhile the enlarged on-current region reduces its specific on-resistance.The simulation results show that compared with the Con.DT SJ LD-MOS,the BV of the DC DT SJ LDMOS has been increased from 549.5 to 705.5 V,and the R_(on,sp) decreased to 23.7 mΩ·cm^(2).

关 键 词：double charge compensation layer super-junction deep trench SIS capacitance 

分 类 号：TN386[电子电信—物理电子学]