一种基于时间域的4倍插值高能效Flash ADC  

A High Power Efficient Flash ADC Based on 4 Fold Time-Domain Interpolation

作　　者：刘建伟 姜俊逸 叶雅倩 杨曼琳 王鹏 王育新[1,2] 付晓君[1,2] 李儒章[1,2] LIU Jianwei;JIANG Junyi;YE Yaqian;YANG Manlin;WANG Peng;WANG Yuxing;FU Xiaojun;LI Ruzhang(National Laboratory of Science and Technology on Analog Integrated Circuit,Chongqing 400060,P.R.China;The 24th Research Institute of China Electronics Technology Group Corp.,Chongqing 400060,P.R.China)

机构地区：[1]模拟集成电路国家级重点实验室,重庆400060 [2]中国电子科技集团公司第二十四研究所,重庆400060

出　　处：《微电子学》2022年第4期519-524,共6页Microelectronics

基　　金：模拟集成电路国家级重点实验室基金资助项目(6142802190101)。

摘　　要：采用65 nm CMOS工艺,基于时间域4倍插值技术,设计了一款6位3.4 GS/s Flash ADC。该插值技术可以将N位Flash ADC的比较器数量从传统的2^(N)-1减少到2^(N-2)。与传统插值技术不同,该技术利用简单的SR锁存器有效地实现了4倍插值因子,而无需额外的时钟和校准硬件开销,在插值阶段只需要校准2^(N-2)个比较器的失调电压。在不同的工艺角、电源电压和温度(PVT)下,SR锁存器中的失调电压不超过±0.5 LSB。该ADC的采样频率达到3.4 GS/s,其在Nyquist输入时的ENOB达到5.4位,在1V电源下消耗12.6 mW的功耗,其Walden FoM值为89 fJ/(conv·step)。A 6-bit 3.4 GS/s flash ADC was designed in a 65 nm CMOS process based on the 4 fold time-domain interpolation technique which allowed the reduction of the number of comparators from the conventional 2^(N)-1 to 2^(N-2)in a N-bit flash ADC.The proposed scheme achieved effectively a 4 fold interpolation factor with simple SR-latches without extra clocking and calibration hardware overhead in the interpolated stage,where only offset between the 2^(N-2)comparators needed to be calibrated.The offset in SR-latches was within±0.5 LSB in the reported ADC under a wide range of process,voltage supply,and temperature(PVT).The prototype achieved 3.4 GS/s sampling frequency with 5.4 bit ENOB at Nyquist and consumed 12.6 mW power at 1 V supply,yielding a Walden FoM of 89 fJ/(conv·step).

关 键 词：Flash ADC 时间比较器 4倍时间域内插技术 SR锁存器 

分 类 号：TN792[电子电信—电路与系统]