基于流水线ADC的MDAC电容失配校准研究  

Research on MDAC Capacitance Mismatch Calibration Based on Pipelined ADC

作　　者：李琨 叶明远 万书芹[1] 何秋秀 LI Kun;YE Mingyuan;WAN Shuqin;HE Qiuxiu(The 58th Research Institute of China Electronics Technology Group Corp.,Wuxi,Jiangsu 214035,P.R.China)

机构地区：[1]中国电子科技集团公司第五十八研究所,江苏无锡214035

出　　处：《微电子学》2022年第4期544-549,共6页Microelectronics

基　　金：国家自然科学基金资助项目(61704161,62174149);江苏省自然科学基金资助项目(BK20211042)。

摘　　要：针对MDAC中采样电容失配会降低ADC输出非线性性能的问题,提出了一种流水线ADC的前台数字校准技术。该前台数字校准技术利用ADC输出积分非线性的相对偏差提取误差,利用简单的多路选择运算单元进行误差补偿。在此基础上,采用Verilog HDL实现了RTL级描述并成功流片。仿真和测试结果表明,该校准算法能够提升ADC输出性能。A foreground digital calibration technology for pipelined ADC was introduced.The calibration was mainly aimed at the sampling capacitor mismatch in MDAC,which increased the nonlinearity of ADC output.The proposed foreground digital calibration technology used the relative deviation of the integral nonlinearity of the ADC output to extract the error,and used a simple multi-channel selection operation unit to compensate the error.On this basis,Verilog HDL was used to realize RTL level description,and the circuit was taped out successfully.Simulation and test results showed that the proposed calibration algorithm could improve the output performance of ADC.

关 键 词：流水线ADC MDAC 采样电容失配 前台数字校准 

分 类 号：TN792[电子电信—电路与系统]