一种超低功耗小面积的Σ-ΔADC数字抽取滤波器  

A Digital Decimation Filter ofΣ-ΔADC with Ultra-Low Power and Small Area

作　　者：申泽生 刘云涛[1,2] 方硕 王云 SHEN Zesheng;LIU Yuntao;FANG Shuo;WANG Yun(Harbin Engineering University,Harbin 150001,P.R.China;Key Laboratory of Advanced Marine Communication and Information Technology,Ministry of Industry and Information Technology,Harbin 150001,P.R.China;Guangdong Greater Area Institute of Integrated Circuit and System,Guangzhou 510535,P.R.China)

机构地区：[1]哈尔滨工程大学,哈尔滨150001 [2]先进船舶通信与信息技术工业和信息化部重点实验室,哈尔滨150001 [3]广东省大湾区集成电路与系统应用研究院,广州510535

出　　处：《微电子学》2022年第4期555-561,共7页Microelectronics

基　　金：国家自然科学基金重大仪器研制项目(62027814);中央高校基本科研业务费专项(3072021CF0806)。

摘　　要：提出并实现了一种针对音频信号Σ-Δ模数转换器的超低功耗和低资源占用的数字抽取滤波器。该滤波器采用多级级联结构,由级联积分梳状滤波器、极简结构补偿器和全通多相型IIR滤波器组成,相较于传统FIR滤波器级联方案,能够以极低的阶数和硬件复杂度实现高倍抽取、极小的通带波纹和高水平的阻带衰减,同时具有近似线性相位特性。整体有效带宽为20 kHz,共完成128倍抽取。采用0.18μm CMOS工艺完成ASIC设计,数字版图面积为0.37 mm^(2),功耗为125μW,信噪比达到98.79 dB,有效位数为16 bit。与传统FIR结构抽取滤波器相比,面积减小了60%,功耗降低了20%。This research presented a digital decimation filter with ultra-low power and small area in the audio signalΣ-Δanalog-to-digital converters.The filter consisted of the cascaded integrating comb filter,the low order compensator,and the all-pass polyphase IIR filter.Compared with the conventional FIR filter,it contained lower orders and hardware complexity.Meanwhile,it could achieve high decimation,ultra-low passband ripple,high stopband attenuation and approximately linear phase.The overall effective bandwidth was 20 kHz,and the decimation factor was 128.The ASIC design was implemented in a 0.18μm CMOS process.The digital layout area was 0.37 mm^(2),and the power was 125μW.The SNR reached 98.79 dB,and the effective accuracy achieved 16 bit.Compared with that of the decimation filter of traditional FIR structure,the area of the proposed digital decimation filter was reduced by 60%and the power consumption was cut down by 20%.

关 键 词：数字抽取滤波器 Σ-Δ模数转换器 低功耗 补偿滤波器 IIR多相滤波器 

分 类 号：TN713.7[电子电信—电路与系统] TN792