一种16位高精度分段式电阻型DAC设计  

A 16-bit High-Precision Segmented-Resistance DAC

作　　者：张皓然 焦子豪 盛炜[1] 章宇新 曹燕杰[1] 陈旻琦 ZHANG Haoran;JIAO Zihao;SHENG Wei;ZHANG Yuxin;CAO Yanjie;CHEN Minqi(The 58th Research Institute of China Electronics Technology Group Corporation,Wuxi,Jiangsu 214000,P.R.China;School of Microelectronics,Xi’an Jiaotong University,Xi’an 710049,P.R.China)

机构地区：[1]中国电子科技集团公司第五十八研究所,江苏无锡214000 [2]西安交通大学微电子学院,西安710049

出　　处：《微电子学》2022年第4期608-613,共6页Microelectronics

基　　金：国家自然科学基金资助项目(62174149);江苏省自然科学基金资助项目(BK20211042)。

摘　　要：采用0.5μm BCD工艺,设计了一种16位分段式电阻型高精度DAC。根据集成电路工艺中电阻的一般失配特性,确定电阻型DAC采用“4+12”的分段结构,分别为高位温度计码结构和低位二进制码结构。整个电路中的电阻类型均采用高阻型电阻,减小了DAC开关结构中的失配,极大降低了整体功耗。电路结构紧凑,整体面积小,仅有2.3976 mm^(2)。结合后仿真结果,对版图进行合理调整,使电路具有较低的微分非线性(DNL),之后采用校正结构,进一步降低DNL。电路测试结果表明,输入数字信号为10 kHz的正弦波时,DAC的无杂散动态范围(SFDR)为57.72 dB,DNL为0.5 LSB,积分非线性(INL)为1 LSB,功耗为1.5 mW。Based on a 0.5μm BCD technology,a 16-bit high-precision segmented-resistance digital-to-analog converter(DAC)was designed.According to the general resistance mismatch feature in integrated circuit process,the DAC had“4+12”architecture,and it was divided into temperature coding part and binary coding part.All the resistors in this DAC were high-impedance,which reduced the mismatch in the DAC switch architecture as well as its whole power dissipation.The DAC had a compact architecture and a small layout area of 2.3976 mm^(2).Combined with the results after post-simulation,the layout was modified,which made the DAC have a low differential non-linearity(DNL).Moreover,its calibration part could make it lower.The test results showed that the DAC had a spurious free dynamic range of 57.72 dB,a DNL of 0.5 LSB,a INL of 1 LSB,and a power dissipation of 1.5 mW when its input was 10 kHz sine digital wave data.

关 键 词：分段式电阻型DAC 温度计码 二进制码 无杂散动态范围 校准模块 

分 类 号：TN792[电子电信—电路与系统]