基于硬件实现的高效率视频编码整像素运动估计算法优化  

Optimization of high efficiency video coding integer motion estimation algorithm based on hardware implementation

作　　者：聂宇鑫 施隆照[1] 黄霖 NIE Yuxin;SHI Longzhao;HUANG Lin(College of Physics and Information Engineering,Fuzhou University,Fuzhou,Fujian 350108,China)

机构地区：[1]福州大学物理与信息工程学院,福建福州350108

出　　处：《福州大学学报（自然科学版）》2022年第5期595-601,共7页Journal of Fuzhou University(Natural Science Edition)

基　　金：2020年福建省高等学校科技创新团队资助项目。

摘　　要：为减少运动估计模块周期数,提高硬件工作效率,从硬件实现的角度对小菱形搜索算法进行优化,调整PU和CU的迭代与处理顺序,解决处理过程中流水线停滞的问题.对小块PU采取并行计算,进一步提高处理速度.用Matlab实现搜索算法,使用Verilog语言描述硬件电路,两个版本在数据上使用相同的激励文件,对比各模块中间值进行功能验证.通过对多组序列的测试,硬件电路对一个64 px×64 px的CTU进行先进的运动矢量预测技术和整像素处理,估计需要平均消耗5800个时钟周期,在QuartusII平台上选中Arria 10AX115N3F40E2SG型号的开发板,主频能够达到186 MHz,整像素运动估计模块综合性能能够达到1080p@61 f·s^(-1).In order to reduce the number of cycles of the motion estimation module and improve hardware efficiency,optimizes the small diamond search algorithm from the perspective of hardware implementation.First,the iteration and processing sequence of PU and CU were adjusted to solve the problem of pipeline stagnation in the process of processing.At the same time,the parallel computing method for small PU blocks can further improve the processing speed.This article first uses Matlab to implement the search algorithm,uses Verilog language to describe the hardware circuit,the two versions use the same excitation file on the data,and compare the intermediate values of each module for functional verification.Through the test of multiple sets of sequences,the hardware circuit of this article needs an average consumption of 5800 clk for AVMP and IME processing on a 64 px×64 px CTU.The Arria 10AX115N3F40E2SG development board is selected on the QuartusII platform,the main frequency can reach 186 MHz,and the overall performance of the whole pixel motion estimation module can reach 1080p@61 f·s^(-1).

关 键 词：高效率视频编码 整像素运动估计 视频编码标准 硬件实现 小菱形搜索算法 

分 类 号：TN941.3[电子电信—信号与信息处理]