一种基于APB总线的单线接口设计  

One-Wire-Interface design based on APB bus

作　　者：徐建皓 万培元 刘胜 陈志杰 李珍 杨江 XU Jianhao;WAN Peiyuan;LIU Sheng;CHEN Zhijie;LI Zhen;YANG Jiang(Beijing Embedded System Laboratory,Information Department,Beijing University of Technology,Beijing 100124,China)

机构地区：[1]北京工业大学信息学部嵌入式系统重点实验室,北京100124

出　　处：《太赫兹科学与电子信息学报》2022年第10期1046-1052,共7页Journal of Terahertz Science and Electronic Information Technology

基　　金：国家电网有限公司总部科技资助项目(5100-201941433A-0-0-00)。

摘　　要：设计了一种基于先进外设接口(APB)总线的单线数字接口(OWI),APB总线可以配置接口参数并读取接口的状态、数据信息,有着较强的灵活性与可监测性。该接口通过一根公用的数据线实现主机与一个或多个从器件之间的半双工双向通信。相比于其他通信接口,线路简单,节约了I/O口资源,降低了硬件成本。本文基于单线传输协议,对数据传输时序以及状态机进行了设计,通过寄存器转换级(RTL)仿真与可编程阵列逻辑(FPGA)验证,结果显示数据可以稳定正确地通过单线接口进行传输,数据传输速率可达100 kHz。An One-Wire-Interface(OWI)based on Advanced Peripheral Bus(APB)is designed.APB bus can configure the data and read the status information of the interface,with strong flexibility and monitoring ability.The interface realizes half-duplex two-way communication between master and one or more slave devices through a common data line.Compared with other communication interfaces,OWI can save I/O port resources and reduce hardware costs.Based on the one wire transmission protocol,the data transmission sequence and state machine are designed.Through Register Transfer Level(RTL)simulation and Field Programmable Gate Array(FPGA)verification,the results show that the data can be stably and correctly transmitted through OWI and the data transmission rate can reach 100 kHz.

关 键 词：单线数字接口 APB总线 状态机 RTL设计 FPGA验证 RTL验证 

分 类 号：TN492[电子电信—微电子学与固体电子学]