基于FPGA的万兆以太网UDP协议通信接口设计  

Design of 10 gigabit ethernet UDP communication module based on FPGA

作　　者：赵世超 左金印 魏骁 赵哲 Zhao Shichao;Zuo Jinyin;Wei Xiao;Zhao Zhe(National Computer System Engineering Research Institute of China,Beijing 100083,China)

机构地区：[1]华北计算机系统工程研究所,北京100083

出　　处：《电子技术应用》2022年第10期113-117,122,共6页Application of Electronic Technique

摘　　要：针对嵌入式设备迅速增长的数据传输需求,介绍了一种依托于现场可编程门阵列(Field Programmable Gate Array,FPGA)平台,以光纤为传输媒介的万兆UDP/IP协议通信接口模块,并探究引入分支预测机制对通信接口模块发送时延产生的影响。通过对现有网络接口层、网际层、传输层和应用层典型传输模型的深入研究,使用硬件描述语言,模块化设计ARP控制器、IP控制器和UDP控制器,实现完备的UDP/IP通信接口模块,并评估了引入分支预测机制对通信接口模块发送时延产生的影响。分析表明:该设计实现简单,适配嵌入式设备对高带宽、低延时、资源低占用的需求,具备自主维护ARP表的能力,支持多设备级联。该设计在高速数据采集、远距离信息传输、片上数据高速处理等应用场景具有积极的意义。In order to solve the rapidly growing data transmission problem for embedded devices,this paper introduces a 10 gigabit UDP/IP protocol communication module,which relies on the Field Programmable Gate Array(FPGA)platform and uses optical fiber as the transmission medium,and explores the impact of introducing the branch prediction mechanism on the transmission delay of the communication interface module.Through in-depth research on the typical transmission model of the existing Open Systems Interconnection(OSI),using hardware description language,the ARP controller,IP controller and UDP controller are modularly designed to form a complete UDP/IP communication module.And the influence of introducing the branch prediction mechanism on the transmission delay of the communication module is evaluated.The analysis shows that the design is simple to implement and adapts to the requirements of embedded devices for high bandwidth,low latency and low resource occupation.It maintains the ARP table independently and supports multi-device cascading.It has positive significance in application scenarios such as high-speed data acquisition,long-distance information transmission,and high-speed processing of on-chip data.

关 键 词：现场可编程门阵列 光纤通信 万兆以太网 UDP/IP协议 分支预测机制 

分 类 号：TN919[电子电信—通信与信息系统]